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  #1 (permalink)  
Old 05-15-2006, 09:07 PM
Pinhas
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Posts: n/a
Default icarus/cver and OpenRISC/or1k (orp_soc) from open core

Hi
Does somebody has experience with this core and free verilog
sorp_socimulators. If so please recommend a fix.

cver compiles and runs it okay. The log files and dump are created. In
VCD dump some signals like of module sram_top are high Z and should be
1/0 (no three state).

icarus crashes during compilation. This is a very big design and I
tried to figure out what is wrong by removing files. I made some
progress but still icarus crashes.

.../../rtl/verilog/xsv_fpga_top.v:1067: warning: Port 7 (wb_adr_i) of
ps2_top expects 4 bits, got 32.
.../../rtl/verilog/xsv_fpga_top.v:1067: : Leaving 28 high bits of
the expression dangling.
.../../bench/verilog/xess_top.v:134544377: warning: Port 26 (vga_r) of
xsv_fpga_top expects 4 bits, got 2.
.../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
of the port unconnected.
.../../bench/verilog/xess_top.v:134544377: warning: Port 27 (vga_g) of
xsv_fpga_top expects 4 bits, got 2.
.../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
of the port unconnected.
.../../bench/verilog/xess_top.v:134544377: warning: Port 28 (vga_b) of
xsv_fpga_top expects 4 bits, got 2.
.../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
of the port unconnected.
.../../bench/verilog/xess_top.v:134544377: warning: Port 40 (eth_txd) of
xsv_fpga_top expects 4 bits, got 5.
.../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
of the expression dangling.
.../../bench/verilog/xess_top.v:134544377: warning: Port 44 (eth_rxd) of
xsv_fpga_top expects 4 bits, got 5.
.../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
of the expression dangling.
ivl: cprop.cc:938: virtual void cprop_functor::lpm_mux(Design*,
NetMux*): Assertion `obj->pin_Data(idx, 0).nexus()->drivers_constant()
&& obj->pin_Data(idx, 1).nexus()->drivers_constant()' failed.
sh: line 1: 19919 Done /usr/local/lib/ivl/ivlpp -L
-D__ICARUS__=1 -f/tmp/ivrlg6a558351 -I../../bench/verilog
-I../../bench/models/28f016s3 -I../../rtl/verilog
-I../../rtl/verilog/mem_if -I../../rtl/verilog/dbg_interface
-I../../rtl/verilog/ssvga -I../../rtl/verilog/ethernet
-I../../rtl/verilog/uart16550 -I../../rtl/verilog/ps2
-I../../rtl/verilog/or1200 -I../../lib/altera
19920 Aborted | /usr/local/lib/ivl/ivl
-C/tmp/ivrlh6a558351 -C/usr/local/lib/ivl/vvp.conf -- -

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  #2 (permalink)  
Old 05-15-2006, 11:18 PM
Stephen Williams
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Posts: n/a
Default Re: icarus/cver and OpenRISC/or1k (orp_soc) from open core

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Hash: SHA1

Pinhas wrote:

> icarus crashes during compilation. This is a very big design and I
> tried to figure out what is wrong by removing files. I made some
> progress but still icarus crashes.


Which version of Icarus Verilog? Have you tried the current snapshot?
What are the flags you are passing to the compiler?

The assertion is tripping while trying to propagate constants through
a MUX device of some sort. Perhaps a ternary in a continuous assign?
In any case, it appears from the assertion that you are using v0.8.*.
Try the latest snapshot. Many bugs are fixed.


> ../../rtl/verilog/xsv_fpga_top.v:1067: warning: Port 7 (wb_adr_i) of
> ps2_top expects 4 bits, got 32.
> ../../rtl/verilog/xsv_fpga_top.v:1067: : Leaving 28 high bits of
> the expression dangling.
> ../../bench/verilog/xess_top.v:134544377: warning: Port 26 (vga_r) of
> xsv_fpga_top expects 4 bits, got 2.
> ../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
> of the port unconnected.
> ../../bench/verilog/xess_top.v:134544377: warning: Port 27 (vga_g) of
> xsv_fpga_top expects 4 bits, got 2.
> ../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
> of the port unconnected.
> ../../bench/verilog/xess_top.v:134544377: warning: Port 28 (vga_b) of
> xsv_fpga_top expects 4 bits, got 2.
> ../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
> of the port unconnected.
> ../../bench/verilog/xess_top.v:134544377: warning: Port 40 (eth_txd) of
> xsv_fpga_top expects 4 bits, got 5.
> ../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
> of the expression dangling.
> ../../bench/verilog/xess_top.v:134544377: warning: Port 44 (eth_rxd) of
> xsv_fpga_top expects 4 bits, got 5.
> ../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
> of the expression dangling.
> ivl: cprop.cc:938: virtual void cprop_functor::lpm_mux(Design*,
> NetMux*): Assertion `obj->pin_Data(idx, 0).nexus()->drivers_constant()
> && obj->pin_Data(idx, 1).nexus()->drivers_constant()' failed.
> sh: line 1: 19919 Done /usr/local/lib/ivl/ivlpp -L
> -D__ICARUS__=1 -f/tmp/ivrlg6a558351 -I../../bench/verilog
> -I../../bench/models/28f016s3 -I../../rtl/verilog
> -I../../rtl/verilog/mem_if -I../../rtl/verilog/dbg_interface
> -I../../rtl/verilog/ssvga -I../../rtl/verilog/ethernet
> -I../../rtl/verilog/uart16550 -I../../rtl/verilog/ps2
> -I../../rtl/verilog/or1200 -I../../lib/altera
> 19920 Aborted | /usr/local/lib/ivl/ivl
> -C/tmp/ivrlh6a558351 -C/usr/local/lib/ivl/vvp.conf -- -
>



- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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  #3 (permalink)  
Old 05-16-2006, 06:33 AM
Pinhas
Guest
 
Posts: n/a
Default Re: icarus/cver and OpenRISC/or1k (orp_soc) from open core

I use version 0.8 for linux. Last time I got problem with XILINX unisim
when using a version from snap shot so I switched back to 0.8 release.
I'll try it with lates snap shot.
Icarus Verilog version 0.8 ($Name: v0_8_1 $)
Copyright 1998-2003 Stephen Williams


This is how I compile (removed audion model because of range errors and
remove altera model):
iverilog -I../../bench/verilog -I../../bench/models/28f016s3
-I../../rtl/verilog -I../../rtl/verilog/mem_if
-I../../rtl/verilog/dbg_interface -I../../rtl/verilog/ssvga
-I../../rtl/verilog/ethernet -y../../rtl/verilog/uart16550
-I../../rtl/verilog/uart16550 -I../../rtl/verilog/ps2
-I../../rtl/verilog/or1200 -I../../lib/xilinx/coregen
-I../../lib/altera -y../../lib/xilinx/unisims -cpk_iver.f -o dut.vvp >&
pk_iver_cmp.txt


ternary in a continuous assign...
Yes I think I saw something like this in the code. I'll try to re-write
it.




Stephen Williams wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> Pinhas wrote:
>
> > icarus crashes during compilation. This is a very big design and I
> > tried to figure out what is wrong by removing files. I made some
> > progress but still icarus crashes.

>
> Which version of Icarus Verilog? Have you tried the current snapshot?
> What are the flags you are passing to the compiler?
>
> The assertion is tripping while trying to propagate constants through
> a MUX device of some sort. Perhaps a ternary in a continuous assign?
> In any case, it appears from the assertion that you are using v0.8.*.
> Try the latest snapshot. Many bugs are fixed.
>
>
> > ../../rtl/verilog/xsv_fpga_top.v:1067: warning: Port 7 (wb_adr_i) of
> > ps2_top expects 4 bits, got 32.
> > ../../rtl/verilog/xsv_fpga_top.v:1067: : Leaving 28 high bits of
> > the expression dangling.
> > ../../bench/verilog/xess_top.v:134544377: warning: Port 26 (vga_r) of
> > xsv_fpga_top expects 4 bits, got 2.
> > ../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
> > of the port unconnected.
> > ../../bench/verilog/xess_top.v:134544377: warning: Port 27 (vga_g) of
> > xsv_fpga_top expects 4 bits, got 2.
> > ../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
> > of the port unconnected.
> > ../../bench/verilog/xess_top.v:134544377: warning: Port 28 (vga_b) of
> > xsv_fpga_top expects 4 bits, got 2.
> > ../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
> > of the port unconnected.
> > ../../bench/verilog/xess_top.v:134544377: warning: Port 40 (eth_txd) of
> > xsv_fpga_top expects 4 bits, got 5.
> > ../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
> > of the expression dangling.
> > ../../bench/verilog/xess_top.v:134544377: warning: Port 44 (eth_rxd) of
> > xsv_fpga_top expects 4 bits, got 5.
> > ../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
> > of the expression dangling.
> > ivl: cprop.cc:938: virtual void cprop_functor::lpm_mux(Design*,
> > NetMux*): Assertion `obj->pin_Data(idx, 0).nexus()->drivers_constant()
> > && obj->pin_Data(idx, 1).nexus()->drivers_constant()' failed.
> > sh: line 1: 19919 Done /usr/local/lib/ivl/ivlpp -L
> > -D__ICARUS__=1 -f/tmp/ivrlg6a558351 -I../../bench/verilog
> > -I../../bench/models/28f016s3 -I../../rtl/verilog
> > -I../../rtl/verilog/mem_if -I../../rtl/verilog/dbg_interface
> > -I../../rtl/verilog/ssvga -I../../rtl/verilog/ethernet
> > -I../../rtl/verilog/uart16550 -I../../rtl/verilog/ps2
> > -I../../rtl/verilog/or1200 -I../../lib/altera
> > 19920 Aborted | /usr/local/lib/ivl/ivl
> > -C/tmp/ivrlh6a558351 -C/usr/local/lib/ivl/vvp.conf -- -
> >

>
>
> - --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
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> Version: GnuPG v1.2.5 (GNU/Linux)
> Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
>
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> 1gUWq6JYQjU/Uwq1gLKPGsI=
> =3uSM
> -----END PGP SIGNATURE-----


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  #4 (permalink)  
Old 05-16-2006, 03:55 PM
Stephen Williams
Guest
 
Posts: n/a
Default Re: icarus/cver and OpenRISC/or1k (orp_soc) from open core

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Hash: SHA1


If you can bundle up and send to me enough scripts/files that I can try
to build this thing, that would be most helpful. I would ideally like to
fix the devel branch, especially if there is a bug triggered by a Xilinx
unisim model. Do you recall which module it was?

You can send files directly to the e-mail address in my signature.


Pinhas wrote:
> I use version 0.8 for linux. Last time I got problem with XILINX unisim
> when using a version from snap shot so I switched back to 0.8 release.
> I'll try it with lates snap shot.
> Icarus Verilog version 0.8 ($Name: v0_8_1 $)
> Copyright 1998-2003 Stephen Williams
>
>
> This is how I compile (removed audion model because of range errors and
> remove altera model):
> iverilog -I../../bench/verilog -I../../bench/models/28f016s3
> -I../../rtl/verilog -I../../rtl/verilog/mem_if
> -I../../rtl/verilog/dbg_interface -I../../rtl/verilog/ssvga
> -I../../rtl/verilog/ethernet -y../../rtl/verilog/uart16550
> -I../../rtl/verilog/uart16550 -I../../rtl/verilog/ps2
> -I../../rtl/verilog/or1200 -I../../lib/xilinx/coregen
> -I../../lib/altera -y../../lib/xilinx/unisims -cpk_iver.f -o dut.vvp >&
> pk_iver_cmp.txt
>
>
> ternary in a continuous assign...
> Yes I think I saw something like this in the code. I'll try to re-write
> it.
>
>
>
>
> Stephen Williams wrote:
> Pinhas wrote:
>
>>>> icarus crashes during compilation. This is a very big design and I
>>>> tried to figure out what is wrong by removing files. I made some
>>>> progress but still icarus crashes.

> Which version of Icarus Verilog? Have you tried the current snapshot?
> What are the flags you are passing to the compiler?
>
> The assertion is tripping while trying to propagate constants through
> a MUX device of some sort. Perhaps a ternary in a continuous assign?
> In any case, it appears from the assertion that you are using v0.8.*.
> Try the latest snapshot. Many bugs are fixed.
>
>
>>>> ../../rtl/verilog/xsv_fpga_top.v:1067: warning: Port 7 (wb_adr_i) of
>>>> ps2_top expects 4 bits, got 32.
>>>> ../../rtl/verilog/xsv_fpga_top.v:1067: : Leaving 28 high bits of
>>>> the expression dangling.
>>>> ../../bench/verilog/xess_top.v:134544377: warning: Port 26 (vga_r) of
>>>> xsv_fpga_top expects 4 bits, got 2.
>>>> ../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
>>>> of the port unconnected.
>>>> ../../bench/verilog/xess_top.v:134544377: warning: Port 27 (vga_g) of
>>>> xsv_fpga_top expects 4 bits, got 2.
>>>> ../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
>>>> of the port unconnected.
>>>> ../../bench/verilog/xess_top.v:134544377: warning: Port 28 (vga_b) of
>>>> xsv_fpga_top expects 4 bits, got 2.
>>>> ../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
>>>> of the port unconnected.
>>>> ../../bench/verilog/xess_top.v:134544377: warning: Port 40 (eth_txd) of
>>>> xsv_fpga_top expects 4 bits, got 5.
>>>> ../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
>>>> of the expression dangling.
>>>> ../../bench/verilog/xess_top.v:134544377: warning: Port 44 (eth_rxd) of
>>>> xsv_fpga_top expects 4 bits, got 5.
>>>> ../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
>>>> of the expression dangling.
>>>> ivl: cprop.cc:938: virtual void cprop_functor::lpm_mux(Design*,
>>>> NetMux*): Assertion `obj->pin_Data(idx, 0).nexus()->drivers_constant()
>>>> && obj->pin_Data(idx, 1).nexus()->drivers_constant()' failed.
>>>> sh: line 1: 19919 Done /usr/local/lib/ivl/ivlpp -L
>>>> -D__ICARUS__=1 -f/tmp/ivrlg6a558351 -I../../bench/verilog
>>>> -I../../bench/models/28f016s3 -I../../rtl/verilog
>>>> -I../../rtl/verilog/mem_if -I../../rtl/verilog/dbg_interface
>>>> -I../../rtl/verilog/ssvga -I../../rtl/verilog/ethernet
>>>> -I../../rtl/verilog/uart16550 -I../../rtl/verilog/ps2
>>>> -I../../rtl/verilog/or1200 -I../../lib/altera
>>>> 19920 Aborted | /usr/local/lib/ivl/ivl
>>>> -C/tmp/ivrlh6a558351 -C/usr/local/lib/ivl/vvp.conf -- -
>>>>

>
> --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."


- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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