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Old 06-13-2005, 03:18 AM
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Default How to view internal signals in post synthesis simulation models (Xilinx ISE)

Hi all,

I'd like to find out How to view internal signals in post synthesis
simulation models generated by Xilinx ISE 6.3.

I synthesized a design and generated post-translate, post-map, and post
P&R Simulation Models. Then I simulated them with ModelSim that is linked
to ISE. However, I was unable to check whether the results are corect
because internal signals and memory names are all chaned by ISE: the
results of the simulation are stored in the internal memory of the design
and there was no signal or memory element that matched the memory I want
to observe.

Please let me know how I can check if Xilinx's ISE post-synthesis models
work correctly, by observing internal memory.

Thanks much in advance!

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