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  #1 (permalink)  
Old 08-12-2004, 03:01 AM
seanzhang
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Default how to simulate verilog with rom in modelsim?

I got error like this in modelsim:
# Loading work.top_tb
# Loading work.top
# Loading work.rom1
# ** Warning: (vsim-3010) [TSCALE] - Module 'rom1' has a `timescale
directive in effect, but previous modules do not.
# Region: /top_tb/top1/rom1_inst
# ** Error: (vsim-3033) D:/my project/FPGA logic/tb1/rom1.v(77):
Instantiation of 'altsyncram' failed. The design unit was not found.
# Region: /top_tb/top1/rom1_inst
# Searched libraries:
# work
# Error loading design


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  #2 (permalink)  
Old 08-12-2004, 03:35 AM
seanzhang
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Default Re: how to simulate verilog with rom in modelsim?

who can provide me a simple example about simulate verilog with rom in
modelsim?
I need it most

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  #3 (permalink)  
Old 08-12-2004, 10:03 AM
Petter Gustad
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Default Re: how to simulate verilog with rom in modelsim?

"seanzhang" <[email protected]> writes:

> I got error like this in modelsim:

....
> Instantiation of 'altsyncram' failed. The design unit was not found.


You need to include the Altera library. You will find this in

[Quartus install directory]/eda/sim_lib/altera_mf.v


Petter

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  #4 (permalink)  
Old 08-12-2004, 06:21 PM
Jason Zheng
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Default Re: how to simulate verilog with rom in modelsim?

seanzhang wrote:

> who can provide me a simple example about simulate verilog with rom in
> modelsim?
> I need it most
>


module pseudo_rom(addr, data)
input [1:0] addr;
output [15:0] data;

reg [15:0] data;

always @ (addr)
case (addr)
2'b00: data <= 16'h0001;
2'b01: data <= 16'h0002;
2'b10: data <= 16'b0003;
2'b11: data <= 16'b0004;
default: data <= 16'b0001;
endcase
endmodule
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  #5 (permalink)  
Old 08-12-2004, 06:23 PM
Jason Zheng
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Default Re: how to simulate verilog with rom in modelsim?

Jason Zheng wrote:

> seanzhang wrote:
>
>> who can provide me a simple example about simulate verilog with rom in
>> modelsim?
>> I need it most
>>

>
> module pseudo_rom(addr, data)
> input [1:0] addr;
> output [15:0] data;
>
> reg [15:0] data;
>
> always @ (addr)
> case (addr)
> 2'b00: data <= 16'h0001;
> 2'b01: data <= 16'h0002;
> 2'b10: data <= 16'b0003;
> 2'b11: data <= 16'b0004;
> default: data <= 16'b0001;
> endcase
> endmodule

btw, anyone knows the best way to synthesize rom with actel FPGA? I'm
using simplicity
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  #6 (permalink)  
Old 08-30-2004, 03:59 AM
seanzhang
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Default I use mif file to initialize the content of memory,but how to simulate?

I compile them,but it seems that mif file is not loaded?
how to do this?I am really really puzzled

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  #7 (permalink)  
Old 09-11-2004, 01:35 AM
pablo aimar
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Default Re: I use mif file to initialize the content of memory,but how to simulate?

"seanzhang" <[email protected]> wrote in message news:<[email protected] alkaboutprogramming.com>...
> I compile them,but it seems that mif file is not loaded?
> how to do this?I am really really puzzled



Hi
have a look at coregen documents of xilinx(ram/rom). you have two
types of memory initialization files -- *.mif and *.coe file.
*.mif file is used for simulation
*.coe file for hardwired initialization after programming.

using *.mif is a old approach.

what i did is assign *.coe file in coregen and generate post layout
simulation model and simulate.

or after assign in coregen you can also do functional simulation.

check this and let me know ?

-rao
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