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Old 07-14-2003, 06:29 AM
Li Yijun
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Default How to simulate and model memory by using verilog?

I use array of verylog to write SRAM. I can verify its logic in
ModelSim. But how to simulate its power consuption and area? Can I use
Synopsys Design_analyzer to do that?Just read my verilog file into
Synopsys.

I appreciate your answer!
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Old 07-15-2003, 03:08 AM
Ajeetha Kumari
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Default Re: How to simulate and model memory by using verilog?

Hi,
Typically memories (especially large ones) are NOT synthesized rather
are obtained as hard macros and used in back end. For simulation
purposes, your memory vendor should provide memory models, for
instance Micron does it. Also, Denali provides more accurate models
based on PLI. And if you are using Verilog-2001, you may want to try
Sparse arrays for memory modeling.

Now about area - as I mentioned before, if you are using memory from
hard macros, your vendor should give the area estimate and also the
power estimate. If you want to do some power computation, try tools
such as Simplex which can do power distribution analysis based on SDF
& netlist.

HTH,
Ajeetha
http://www.noveldv.com

Li Yijun <[email protected]> wrote in message news:<[email protected]>...
> I use array of verylog to write SRAM. I can verify its logic in
> ModelSim. But how to simulate its power consuption and area? Can I use
> Synopsys Design_analyzer to do that?Just read my verilog file into
> Synopsys.
>
> I appreciate your answer!

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  #3 (permalink)  
Old 07-17-2003, 02:08 AM
Steven Sharp
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Default Re: How to simulate and model memory by using verilog?

[email protected] (Ajeetha Kumari) wrote in message news:<[email protected] com>...

> And if you are using Verilog-2001, you may want to try
> Sparse arrays for memory modeling.


I am not aware of any support for sparse arrays in Verilog-2001.
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Old 07-26-2003, 06:37 AM
Ajeetha Kumari
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Default Re: How to simulate and model memory by using verilog?

Hi,
Thanks for correcting me, yes I mixed up reading that VCS supports
sparse array to LRM, apologies. BTW, does Cadence intend to support
something similar without the $damem?

Thanks,
Ajeetha
http://www.noveldv.com

[email protected] (Steven Sharp) wrote in message news:<[email protected] com>...
> [email protected] (Ajeetha Kumari) wrote in message news:<[email protected] com>...
>
> > And if you are using Verilog-2001, you may want to try
> > Sparse arrays for memory modeling.

>
> I am not aware of any support for sparse arrays in Verilog-2001.

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  #5 (permalink)  
Old 07-27-2003, 06:13 AM
Steven Sharp
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Default Re: How to simulate and model memory by using verilog?

[email protected] (Ajeetha Kumari) wrote in message news:<[email protected] com>...
> Thanks for correcting me, yes I mixed up reading that VCS supports
> sparse array to LRM, apologies. BTW, does Cadence intend to support
> something similar without the $damem?


It is on our list of things we would like to support in NC-Verilog.
We have had some customer requests for it, and it is easy to see
that it would be very useful. It is just a matter of prioritizing
it against the other things we have to do. For example, while our
next release will almost finish our Verilog-2001 support, there
are still a few things to be done on it.
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Old 07-30-2003, 08:35 PM
Prasanna
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Default Re: How to simulate and model memory by using verilog?

[email protected] (Steven Sharp) wrote in message news:<[email protected] com>...
> [email protected] (Ajeetha Kumari) wrote in message news:<[email protected] com>...
> > Thanks for correcting me, yes I mixed up reading that VCS supports
> > sparse array to LRM, apologies. BTW, does Cadence intend to support
> > something similar without the $damem?

>
> It is on our list of things we would like to support in NC-Verilog.
> We have had some customer requests for it, and it is easy to see
> that it would be very useful. It is just a matter of prioritizing
> it against the other things we have to do. For example, while our
> next release will almost finish our Verilog-2001 support, there
> are still a few things to be done on it.


Intresting discussion... Just want to add a little here... Most of the
time, when people use large memories, they are aware of who their ASIC
vendor is going to be and get memory models, hardcore black boxes etc.
However, if someone intends to use a fixed memory block (such as ones
available on FPGAs EBRs or block rams), they already know what it is.
In an other case of distributed ram (flop based), used for small
buffers, pipelining and very small depth FIFOs, some people use arrays
for which they can actually use library_compiler commands such as
report_lib for the flops and get the numbers for the cell.

- Prasanna
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