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-   -   How to find if two nets are connected in PLI (http://www.fpgacentral.com/group/showthread.php?t=43943)

Arash 04-01-2004 01:44 AM

How to find if two nets are connected in PLI
Suppose two modules mod1 and mod2 definitions are as follows:

mod1 (output a);
mod2 (input b);

Assume that they are instantiated in module top and are conncted as

module top;
wire i;
mod1 m1 (i);
mod2 m2 (i)

The problem is that I needed to find this out dynamically through PLI
routines within mod1 and mod2. That is, we should know if two ports
are connected to each other at simulation time in PLI routines.
The solution I used was using acc_handle_simulated_net function. I
called a PLI routine within each mod1 and mod2 as follows:

mod1 (output a);

$Save PLI routine saves the simulation net handle of a in global
memory. If we do this also in mod2, since the simulation net handle of
a and b (b is in mod2) is the same, by comparing them we can find out
that they are connected to each other (i.e they are on the same net).
This is done by using the fact that simulators can make collapsed nets
and simulation nets as described in IEEE 1364 standard. However, some
simulators don't do this at all, or at some situations. For example,
in cadence NCVerilog, if you use force in your always blocks, the
simulator doesn't make simulation nets.
So, my question is that given the handles of two wires in separate
modules, is there any other way that we can find out if they are on
the same net (i.e. connected to each other)? In other words, is there
an equivalent function for acc_handle_simulated_net that always works?

I would appreciate your answers.

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