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Old 07-18-2007, 07:55 AM
Ssa
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Default How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?

I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera
Quurtus II 7.1. (It just took a few simple RTL-edits.)

But what about the JTAG-debug unit? It seems to use the Lattice's
JTAG-block.
Can I just replace this with a generic JTAG TAP-controller, and then use a
Xilinx-hosted Mico32 with a Lattice download-cable?


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Old 07-19-2007, 07:26 PM
Antti
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Default Re: How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?

On 18 Jul., 07:55, "Ssa" <[email protected]> wrote:
> I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera
> Quurtus II 7.1. (It just took a few simple RTL-edits.)
>
> But what about the JTAG-debug unit? It seems to use the Lattice's
> JTAG-block.
> Can I just replace this with a generic JTAG TAP-controller, and then use a
> Xilinx-hosted Mico32 with a Lattice download-cable?


if you rebuild the lattice jtag-tap then yes. but you have to use
fpga regular io pads, not xilinx bscan

antti

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