On Jun 5, 4:51*pm, shwetika <
[email protected]> wrote:
The problem that is causing the error is that you are assigning to a
variable with a continuous assignment. In Verilog (as opposed to
SystemVerilog), continuous assignments are only allowed to nets. And
there are no nets of type real. The easiest way to do this is to stop
storing the intermediate real values in variables and just do the
entire thing in one more complex expression. Vector input in, and
vector output out, and all operations done by applying function calls
to the results of function calls.
I also assume that your input is supposed to be a real value passed in
using a vector and $realtobits. So you need to convert it back to a
real before passing it to $sin. Otherwise it will get treated as a
large integer, and converted to the real number that is closest to
that integer, rather than the one that has the same bit
representation.