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  #26 (permalink)  
Old 03-02-2006, 09:11 AM
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Default Re: How do I make dual-port RAM from single port RAM?

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John_H wrote:
> Frank @ CN wrote:
> > Hi, there:
> >
> > In my application, a RAM needs to be written/read from two sets of
> > data/address ports
> > simultaneously. However, in the ASIC library I can only instantiate some
> > single port RAM
> > and RAM which can be written in one port and read from the other port.
> >
> > How shall I solve this problem?
> >
> > Thank you.

>
> You might get a better idea of the particulars by looking at a data
> sheet for IDT dual-port memories. (www.idt.com)


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  #27 (permalink)  
Old 03-02-2006, 09:13 AM
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Default Re: How do I make dual-port RAM from single port RAM?

Senior Library Design Engineer (NEW) The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.
5+ years industrial experience designing CMOS VLSI standard cell
libraries.
Full understanding of the ASIC design flow and the role of standard
cell libraries.
Experienced in full custom design and layout.
Knowledge of the cell characterization process.
Basic understanding of silicon processing technology.
Understanding of place and route tools, and how they work.
Comfortable with the Linix operating system and strong programming
skills in perl.
Experience working with silicon foundries, preferably TSMC.
Full understanding of the following IC Design tools:
HSPICE
Verilog logic simulation
Cadence Composer
Cadence Virtuoso
Synopsys Design Compiler
A proven track record of successful design projects - completed on
schedule.
Excellent communication skills.
Leadership skills and a personal commitment to the team's success are
also required attributes
Junior Library Design Engineer (NEW) The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.
3+ years industrial experience designing CMOS digital circuits.
Understanding of circuit simulation with SPICE.
Experienced with physical design rules and IC layout.
Knowledge of the Cadence design tools.
Some experience with Verilog modeling and synthesis tools.
Good computer skills and moderate programming experience with perl.
Strong team member with positive learning attitude.
Good oral and written communication skills.
What we expect from you:
If you find this opening interesting then kindly forward your profile
in word format along with your current CTC & expected CTC details to
[email protected] ASAP. Kindly inform the same to your
colleagues and friends.



Thanks & Regards,

Komal Tripathi.

____________________________

PriorityONE Consulting

Your Success is our PRIORITY # 1!

Contact me:

India Mobile: +91-9945341452.

Direct Lines: 080-41313872

E-mail: [email protected]



PriorityONE Consulting provides the best technical talent to suit the
needs of

high end software companies for the entire technology and hierarchy
spectrum.

We serve our clients and our candidates with respect and commitment.

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  #28 (permalink)  
Old 03-02-2006, 09:48 AM
Josep Durán
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Default Re: How do I make dual-port RAM from single port RAM?


"Ulf Samuelsson" <[email protected]> escribió en el mensaje
news:[email protected]
>
>
> You can instantiate FOUR rams and implement a valid bit for each location
> in a register.
> PortA can write to RAM0,RAM1 and read from RAM0 and RAM2
> PortB can write to RAM2,RAM3 and read from RAM1 and RAM3
>
> When PortA writes to address position 17, both RAM0[17] and RAM1[17] are
> updated and the
> VALID_BIT[17] is set to 0 indicating that RAM0,1 are valid instead of
> RAM2,3.
>
> When PortB reads address position 17, both RAM1 and RAM3 are read.
> A multiplexer on the output is controlled by the selected VALID_BIT,
> and since VALID_BIT[17] is zero, it will select the output of RAM1 over
> RAM3.
>
> Obviously this is going to use some gates,so it is not practical for large
> SRAMs.
> Running the RAM at 2 x frequency is going to cost a lot less.
>
>


Following the previous example, I fail to see how can I read PortB address
17
(last time written through portA) while PortA is writing adddress (say) 22.

Am I missing something ?



Regards

Josep Duran



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  #29 (permalink)  
Old 03-02-2006, 04:48 PM
John_H
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Default Re: How do I make dual-port RAM from single port RAM?

Use 2 1Wr2Rd RAMs that are in your library.

Rather than writing a value to both RAMs, write the XOR of the read
value from the other RAM with the write data. To read the valid data,
read the value in both RAMs and XOR them. The read XOR will provide
the last data written to that location. This gets you most of the way.

If you have a write to both ports at the same address - invalid in some
dual-port memories - collision arbitration needs to decide who gets the
write; the winning RAM writes, the losing RAM doesn't. If both RAMs
write in a collision, the data is invalid.

If you guarantee that two writes to the same location never occur at
the same time, the only constraint is that writes to the same address
are never too close (write data becomes valid for read in RAM1 before
RAM2 uses the read data to update that address in RAM2).

This should give you 100% dual-port RAM without too much trouble. You
then only need to worry about the 1Wr2Rd RAM behavior as far as async
vs sync read-first versus sync write-first.

Yay?

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  #30 (permalink)  
Old 03-03-2006, 02:24 AM
rhnlogic
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Posts: n/a
Default Re: How do I make dual-port RAM from single port RAM?

Frank @ CN wrote:
> In my application, a RAM needs to be written/read from two sets of
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some
> single port RAM
> and RAM which can be written in one port and read from the other port.
>
> How shall I solve this problem?


If you have a faster clock available, one common way to solve
this kind of problem is to time-division multiplex the 1-ported RAM.
Essentially run two (or more) successive memory read/write
cycles one the ASIC, per one read/write time slot on the FPGA.

You can also use this technique inside an FPGA to make the
fast dual-port RAMs look like 4 or more ported, but slower,
memories.


IMHO. YMMV.
--
rhn A.T nicholson d.0.t C-o-M

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  #31 (permalink)  
Old 03-03-2006, 07:10 PM
Derek Simmons
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Default Re: How do I make dual-port RAM from single port RAM?

I haven't had time to load Xilinx's tools (sometime I'm going to have
to do it for another project) to see what there DPRAM library device
looks like.

The solution I was going to offer was going to be a time division
solution like rhnlogic suggested. Relative to the reading/writing of
the ports of the DPRAM, what clocks are available? What other controls
signals are present that could be taken advantage of?

If you want to reinvent the wheel you could implement your own dual
port memory. It would probably be a little bit more than 6240 flip
flops if you can limit the address to 130 range and if you're sloppy
about it 16384 flip flops for the whole 256 range. (plus addressing and
control support)

Derek

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  #32 (permalink)  
Old 03-05-2006, 01:43 AM
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Default Re: How do I make dual-port RAM from single port RAM?

When you wrote PortA address 17, you wrote into address 17 of RAM0 and
RAM1. You also wrote 0 (meaning A is valid) into address 17 of
VALID_BIT. When you read PortB address 17, you read address 17 of RAM1
and RAM3. You also read address 17 of VALID_BIT, which gives you back
0, telling you to select the output of RAM1. This gives you the value
you just wrote to RAM1 when you wrote to PortA address 17.

If you had written to address 17 via PortB last, then address 17 of
VALID_BIT would have been set to 1, telling you to select the output of
RAM3 instead. This would have been correct, since a write to portB
would have written to RAM2 and RAM3. If you read portA address 17, you
will read address 17 of RAM0 and RAM2 instead, and selected between
those based on VALID_BIT.

Or perhaps what you are missing is that each of these RAMs has a read
port and a write port, which can be used simultaneously with
independent addresses. This was one of the components that was
described as being available. So PortB can be reading address 17 of
RAM1 at the same time PortA is writing address 22 of RAM1.

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  #33 (permalink)  
Old 03-05-2006, 01:58 AM
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Default Re: How do I make dual-port RAM from single port RAM?

Another clever solution. This requires the same amount of RAM as Ulf's
scheme, but without requiring the 2Rd/2Wr VALID_BIT array. However, it
may require a longer write cycle time, to allow completing the
associated read and XOR with enough setup time for the write. But part
of the write can overlap the read, so it should still be faster than
the time-multiplexing approaches.

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  #34 (permalink)  
Old 03-05-2006, 02:55 AM
John_H
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Default Re: How do I make dual-port RAM from single port RAM?

[email protected] wrote:
> Another clever solution. This requires the same amount of RAM as Ulf's
> scheme, but without requiring the 2Rd/2Wr VALID_BIT array. However, it
> may require a longer write cycle time, to allow completing the
> associated read and XOR with enough setup time for the write. But part
> of the write can overlap the read, so it should still be faster than
> the time-multiplexing approaches.


What I did forget is that the memory may be synchronous read and write.
If the read is asynchronous then this method still works but youre
comment on timing is well taken. In the FPGA there's a nice, small
setup time for memory address and data. An asynchronous read would
require the address access time before that XOR. If the translation is
from FPGA to ASIC, there may be enough margin in the timing to specify
the read access and XOR from the address and the XOR alone from the data
before the write strobe.

If the ASIC memory is synchronous read without the async data, this
method would require more RAMs and some feedback to account for
just-written addresses.

Is the memory 1Wr/2Rd memory primitive an asynchronous read?
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  #35 (permalink)  
Old 03-06-2006, 12:33 PM
Josep Durán
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Default Re: How do I make dual-port RAM from single port RAM?


<[email protected]> escribió en el mensaje
news:[email protected] oups.com...
>
> Or perhaps what you are missing is that each of these RAMs has a read
> port and a write port, which can be used simultaneously with
> independent addresses. This was one of the components that was
> described as being available. So PortB can be reading address 17 of
> RAM1 at the same time PortA is writing address 22 of RAM1.
>



After reading your post I went back to the OP, and it was _clearly_ stated
the availability of such a component.

Thank you for pointing it out.



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