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-   -   How do I make dual-port RAM from single port RAM? (http://www.fpgacentral.com/group/showthread.php?t=45278)

Frank @ CN 02-28-2006 11:58 AM

How do I make dual-port RAM from single port RAM?
 
Hi, there:

In my application, a RAM needs to be written/read from two sets of
data/address ports
simultaneously. However, in the ASIC library I can only instantiate some
single port RAM
and RAM which can be written in one port and read from the other port.

How shall I solve this problem?

Thank you.




Michael Schöberl 02-28-2006 12:17 PM

Re: How do I make dual-port RAM from single port RAM?
 
> In my application, a RAM needs to be written/read from two sets of
> data/address ports simultaneously.


estimate your worst case data rates and take a ram with
the sum of these data-rates (plus overhead) ...

then you need to build some logic to switch between
Port A and B to transfer concurrent access to a
sequential access scheme


bye,
Michael

John_H 02-28-2006 02:23 PM

Re: How do I make dual-port RAM from single port RAM?
 
Frank @ CN wrote:
> Hi, there:
>
> In my application, a RAM needs to be written/read from two sets of
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some
> single port RAM
> and RAM which can be written in one port and read from the other port.
>
> How shall I solve this problem?
>
> Thank you.


You might get a better idea of the particulars by looking at a data
sheet for IDT dual-port memories. (www.idt.com)

JJ 02-28-2006 03:52 PM

Re: How do I make dual-port RAM from single port RAM?
 
For some applications 2 Srams can be used in an alternate buffer
configuration. I assume your 2 ports have similar issue rates otherwise
you may have to mux in time.


Peter Alfke 02-28-2006 04:29 PM

Re: How do I make dual-port RAM from single port RAM?
 
Frank, you posted this in the FPGA newsgroup.
In FPGAs, most RAM structures are naturally dual-ported, e.g. the
Virtex BlockRAMs.
You get two ports, whether you asked for it or not!
Peter Alfke, Xilinx Applications.

Frank @ CN wrote:
> Hi, there:
>
> In my application, a RAM needs to be written/read from two sets of
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some
> single port RAM
> and RAM which can be written in one port and read from the other port.
>
> How shall I solve this problem?
>
> Thank you.



[email protected] 02-28-2006 10:47 PM

Re: How do I make dual-port RAM from single port RAM?
 
For dual read ports and a single write port, this is easy. You just
use two RAMs and always write to both of them together, but read from
them separately, with each treated as a separate read port. For dual
write ports, it gets a lot harder.


Frank @ CN 02-28-2006 10:53 PM

Re: How do I make dual-port RAM from single port RAM?
 

"Peter Alfke" <[email protected]> wrote in message
news:[email protected] oups.com...
> Frank, you posted this in the FPGA newsgroup.
> In FPGAs, most RAM structures are naturally dual-ported, e.g. the
> Virtex BlockRAMs.
> You get two ports, whether you asked for it or not!
> Peter Alfke, Xilinx Applications.
>


Yeah, the original codes are designed with Xilinx DPRAM with a functional
testbenches,
now I need to convert the codes into ASIC implementation. The tougher part
of it is, I
have little understanding of the functionality of the design.



Frank @ CN 02-28-2006 10:54 PM

Re: How do I make dual-port RAM from single port RAM?
 

<[email protected]> wrote in message
news:[email protected] ps.com...
> For dual read ports and a single write port, this is easy. You just
> use two RAMs and always write to both of them together, but read from
> them separately, with each treated as a separate read port. For dual
> write ports, it gets a lot harder.
>


Yeah, there are RAMs in the ASIC library supporting dual read/single write.
I need to make dual read/write out of it. How can I do it now?

Thanks.



[email protected] 02-28-2006 11:32 PM

Re: How do I make dual-port RAM from single port RAM?
 
As someone else suggested, you could time-multiplex the two ports,
which will take a double-speed clock and extra logic for the
multiplexing. And this assumes that you are treating this as a
synchronous RAM.

And someone else suggested that you look at your application and see
whether you really need a full dual-port RAM, or whether you are
dealing with a special case where you can segregate it into independent
parts.

You could build the memory from multiple smaller RAMs and add decode
logic to allow you to do two writes, as long as the writes were to
separate RAMs. If they weren't, one of them would have to wait until
the next cycle. This requires that the other logic trying to do the
write be able to wait if the memory was "busy". Note that real
dual-port memories are effectively implemented this way, except that
the RAM granularity is a single word in the memory. The designers of
those have the advantage that they are designing all the decode logic,
down to the word level.

You can reduce the chance of collisions in this scheme by choosing
which address bits select a RAM and which ones select a word in the
RAM, if you know something about the likely access patterns. For
example, it may be more likely that two memory writes are going to the
same half of the memory than that they are both going to even (or odd)
addresses.

If you can't multiplex, and can't deal with collisions, then you are
out of luck. If you want to use predefined RAMs with their predefined
single-port decoding logic, then you are stuck. Getting true dual-port
requires specialized decode logic in the RAM.


Peter Alfke 03-01-2006 03:07 AM

Re: How do I make dual-port RAM from single port RAM?
 
Sounds like a powerful FPGA argument:
Ifyou really need a true dual-port memory (read and write from either
or both ports simultaneously), you are out-of-luck in the ASIC world,
but you can do this just fine in FPGAs.
Nice to know we have such an edge...
Peter Alfke, Xilinx


Ulf Samuelsson 03-01-2006 05:58 AM

Re: How do I make dual-port RAM from single port RAM?
 

"Frank @ CN" <[email protected]> skrev i meddelandet
news:[email protected]
> Hi, there:
>
> In my application, a RAM needs to be written/read from two sets of
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some
> single port RAM
> and RAM which can be written in one port and read from the other port.
>
> How shall I solve this problem?
>
> Thank you.
>
>



You can instantiate FOUR rams and implement a valid bit for each location in
a register.
PortA can write to RAM0,RAM1 and read from RAM0 and RAM2
PortB can write to RAM2,RAM3 and read from RAM1 and RAM3

When PortA writes to address position 17, both RAM0[17] and RAM1[17] are
updated and the
VALID_BIT[17] is set to 0 indicating that RAM0,1 are valid instead of
RAM2,3.

When PortB reads address position 17, both RAM1 and RAM3 are read.
A multiplexer on the output is controlled by the selected VALID_BIT,
and since VALID_BIT[17] is zero, it will select the output of RAM1 over
RAM3.

Obviously this is going to use some gates,so it is not practical for large
SRAMs.
Running the RAM at 2 x frequency is going to cost a lot less.




--
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may bot be shared by my employer Atmel Nordic AB



JJ 03-01-2006 07:03 AM

Re: How do I make dual-port RAM from single port RAM?
 
So if you are back porting from FPGA to ASIC something stands out right
away which makes this even more messy. Your logic & wiring paths will
now gain significantly in performance but a comparable DPRAM is similar
in performance between ASIC and FPGA for same feature and memory sizes
since they are the same thing (almost). Perhaps there is an option to
double up processing on the logic side rather than try to double up on
SPRAM side.

At this point I can only suggest before continuing with the ASIC, redo
the FPGA design so that it also only uses 1 port atleast you don't burn
masks, tie your hand behind your back on the cheap. Then it should be
easier to convert, atleast you can prove the redesign before
conversion.

Your other option if you really really must use 2 concurrent writes
with no other possibility is to go and get a DP WW RAM core from one of
the ASIC IP houses, Mentor, Cadence, Synopsys and a couple of others
come to mind, not sure who has which. I thought most of the asian
foundries would include such blocks in their library, otherwise it
seems you have a limited library.

So what is the application, & size of DP WW RAM ?

John


JJ 03-01-2006 10:05 AM

Re: How do I make dual-port RAM from single port RAM?
 
The reason I ask for DP WW size is that for applications in say DSP and
data buffering, the memory size might be large but there are possible
options in architecture.

In say a cpu datapath design with a N way ported register file the
options may be far fewer but the size may be much smaller and ameniable
to brute force as suggested by the 4 way Ulf design. That probably
requires that a DP WW store stiil needs to be built but only for 1 bit
direction flag and to the granularity of words or super words if I
understand it right.

John


Sean Burroughs 03-01-2006 03:12 PM

Re: How do I make dual-port RAM from single port RAM?
 
I just converted a quad port 2r2w to F/Fs this morning; luckily, it
was easy to simplify. You don't give enough info - are the clocks
related? How big is it? Do you have higher frequency clocks available?

Curious that you should have a library with no 2rw memories in it. Can
you tell us whose it is? It sounds like it may too new to be usable.

Sean

Derek Simmons 03-01-2006 04:26 PM

Re: How do I make dual-port RAM from single port RAM?
 
I've been trying to follow your problem and now have time to lend some
help. I'm going to approach this from a black-box design point of view.


First question is how are in implementing it or what language are you
using (VHDL, Verilog or something else)?

What size device are you looking to create (data and address bus
width)? Or are you trying to create a library device?

What device and signals in the original design being used?

Derek


[email protected] 03-01-2006 05:57 PM

Re: How do I make dual-port RAM from single port RAM?
 
Presumably this depends on what ASIC libraries you have. There is no
inherent reason that an ASIC library could not include dual-port
memories. Apparently the original poster's didn't.


[email protected] 03-01-2006 06:03 PM

Re: How do I make dual-port RAM from single port RAM?
 
That is a clever solution that I hadn't thought of. Of course, your
VALID_BIT array needs the capabilities of a true dual-port memory. So
this doesn't really build a dual-port memory just out of RAMs. It
builds it from 4 RAMs and a smaller dual-port memory (just as many
elements, but only 1 bit wide). You would have to build that smaller
dual-port memory out of flip-flops. The result still might be smaller
than building the full-size memory out of flip-flops.


Frank 03-02-2006 01:59 AM

Re: How do I make dual-port RAM from single port RAM?
 

<[email protected]> wrote in message
news:[email protected] ups.com...
> Presumably this depends on what ASIC libraries you have. There is no
> inherent reason that an ASIC library could not include dual-port
> memories. Apparently the original poster's didn't.
>


True, some TSMC ASIC libraries had dual-read/write memories, and they used
to provide
memory generators which enables creating the memory blocks of any capacity.

After we changed foundry, things got really complicated. In the new library,
only a few memories
are provided and the width & depth are also fixed. It becomes very
inefficient to use these RAMs.

I guess I am out of luck on memory issues this time.




Frank 03-02-2006 02:10 AM

Re: How do I make dual-port RAM from single port RAM?
 

<[email protected]> wrote in message
news:[email protected] oups.com...
> That is a clever solution that I hadn't thought of. Of course, your
> VALID_BIT array needs the capabilities of a true dual-port memory. So
> this doesn't really build a dual-port memory just out of RAMs. It
> builds it from 4 RAMs and a smaller dual-port memory (just as many
> elements, but only 1 bit wide). You would have to build that smaller
> dual-port memory out of flip-flops. The result still might be smaller
> than building the full-size memory out of flip-flops.
>


Morning Samuelsson & sharp, I haven't got time to study the sequence of the
clever
solution yet. I want to know is, does it have the function of a full dual
port R/W RAM
if the R/W accesses of both ports are random? My RAM is 130*6bit, and the IP
uses
eight pieces of this RAM.

TIA




[email protected] 03-02-2006 04:32 AM

Re: How do I make dual-port RAM from single port RAM?
 
Yes, Ulf's solution gives full dual-port functionality for arbitrary
addresses (though of course you have to decide which port gets the last
word in case of simultaneous writes to the same address, as with any
dual-port memory).

But with your small word size of 6 bits, this may not be
cost-effective. The VALID_BIT array requires similar logic to a
1-bit-wide dual-port memory (not quite the same, since port 0 always
writes a value of 0 and port 1 always writes a value of 1). So you
have to design something close to a 130*1bit dual-port memory out of
flip-flops and logic, and use that with four 130*6bit RAMs (or two
130*6bit dual-read/single-write RAMs, since you indicated you have
those). You might be as well off to design a 130*6bit dual-port memory
from flip-flops and logic.


Kim Enkovaara 03-02-2006 07:36 AM

Re: How do I make dual-port RAM from single port RAM?
 
Peter Alfke wrote:
> Sounds like a powerful FPGA argument:
> Ifyou really need a true dual-port memory (read and write from either
> or both ports simultaneously), you are out-of-luck in the ASIC world,
> but you can do this just fine in FPGAs.
> Nice to know we have such an edge...


That is completely dependent on the ASIC libraries. In FPGA you are out of
luck with higer amount of ports that are available in some ASIC libraries.
For example in the ASIC library I use there are: single port, 1 read 1 write,
dual port and 4-port memories. And then different versions of those
(density, power, speed).

--Kim

Frank 03-02-2006 08:13 AM

Re: How do I make dual-port RAM from single port RAM?
 

"Derek Simmons" <[email protected]> wrote in message
news:[email protected] ups.com...
> I've been trying to follow your problem and now have time to lend some
> help. I'm going to approach this from a black-box design point of view.
>
>
> First question is how are in implementing it or what language are you
> using (VHDL, Verilog or something else)?
>
> What size device are you looking to create (data and address bus
> width)? Or are you trying to create a library device?
>
> What device and signals in the original design being used?
>
> Derek
>


Thank you Derek.
I received an FPGA design in RTL Verilog and need to convert into ASIC. Now
everything is done except this memory issue. The design of the RTL is
unfamiliar to
me so large modifications are meant only for the long run. Requesting
redesign of
the memory isn't an option either.

The culprit RAMs are 8 instances of 130*6bit DPRAM. My entire design is 200K
gate without RAM. My short term goal is to use the existing RAMs in the ASIC
library and perform successful synthesis & gate level simulation, with ASIC
RAMs
included in the system (I could simulate with Xilinx RAM and ASIC for the
rest).

What ideas do you have for my description?




JJ 03-02-2006 08:49 AM

Re: How do I make dual-port RAM from single port RAM?
 
130 by 6 is pretty tiny to have used a whole 4K or 18k bit DPRAM but
the DP feature makes it a job already done.

Are the 8 rams independant copies of the same DP R/W design?
And 130 is a bit odd isn't it?

For this size of this problem the 4 way Ulf design doesn't look so bad
assuming you can compile 130 by 6 arrays, I'd imagine they will be
bigger. Now you only need 130 DP flags to resolve valid words.

John


[email protected] 03-02-2006 09:06 AM

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E-mail: [email protected]



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Visit us at:

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Frank @ CN wrote:
> Hi, there:
>
> In my application, a RAM needs to be written/read from two sets of
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some
> single port RAM
> and RAM which can be written in one port and read from the other port.
>
> How shall I solve this problem?
>
> Thank you.



[email protected] 03-02-2006 09:07 AM

Re: How do I make dual-port RAM from single port RAM?
 
What we expect from you:
If you find this opening interesting then kindly forward your profile
in word format along with your current CTC & expected CTC details to
[email protected] ASAP. Kindly inform the same to your
colleagues and friends.



Thanks & Regards,

Komal Tripathi.

____________________________

PriorityONE Consulting

Your Success is our PRIORITY # 1!

Contact me:

India Mobile: +91-9945341452.

Direct Lines: 080-41313872

E-mail: [email protected]



PriorityONE Consulting provides the best technical talent to suit the
needs of

high end software companies for the entire technology and hierarchy
spectrum.

We serve our clients and our candidates with respect and commitment.



Visit us at:

www.priorityoneindia.com



For Hottest jobs round the globe please register in :

http://finance.groups.yahoo.com/group/jobs_priorityone/


Michael Schöberl wrote:
> > In my application, a RAM needs to be written/read from two sets of
> > data/address ports simultaneously.

>
> estimate your worst case data rates and take a ram with
> the sum of these data-rates (plus overhead) ...
>
> then you need to build some logic to switch between
> Port A and B to transfer concurrent access to a
> sequential access scheme
>
>
> bye,
> Michael



[email protected] 03-02-2006 09:11 AM

Re: How do I make dual-port RAM from single port RAM?
 
Senior Library Design Engineer (NEW) The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.
5+ years industrial experience designing CMOS VLSI standard cell
libraries.
Full understanding of the ASIC design flow and the role of standard
cell libraries.
Experienced in full custom design and layout.
Knowledge of the cell characterization process.
Basic understanding of silicon processing technology.
Understanding of place and route tools, and how they work.
Comfortable with the Linix operating system and strong programming
skills in perl.
Experience working with silicon foundries, preferably TSMC.
Full understanding of the following IC Design tools:
HSPICE
Verilog logic simulation
Cadence Composer
Cadence Virtuoso
Synopsys Design Compiler
A proven track record of successful design projects - completed on
schedule.
Excellent communication skills.
Leadership skills and a personal commitment to the team's success are
also required attributes
Junior Library Design Engineer (NEW) The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.
3+ years industrial experience designing CMOS digital circuits.
Understanding of circuit simulation with SPICE.
Experienced with physical design rules and IC layout.
Knowledge of the Cadence design tools.
Some experience with Verilog modeling and synthesis tools.
Good computer skills and moderate programming experience with perl.
Strong team member with positive learning attitude.
Good oral and written communication skills.
What we expect from you:
If you find this opening interesting then kindly forward your profile
in word format along with your current CTC & expected CTC details to
[email protected] ASAP. Kindly inform the same to your
colleagues and friends.



Thanks & Regards,

Komal Tripathi.

____________________________

PriorityONE Consulting

Your Success is our PRIORITY # 1!

Contact me:

India Mobile: +91-9945341452.

Direct Lines: 080-41313872

E-mail: [email protected]



PriorityONE Consulting provides the best technical talent to suit the
needs of

high end software companies for the entire technology and hierarchy
spectrum.

We serve our clients and our candidates with respect and commitment.



Visit us at:

www.priorityoneindia.com



For Hottest jobs round the globe please register in :

http://finance.groups.yahoo.com/group/jobs_priorityone/


John_H wrote:
> Frank @ CN wrote:
> > Hi, there:
> >
> > In my application, a RAM needs to be written/read from two sets of
> > data/address ports
> > simultaneously. However, in the ASIC library I can only instantiate some
> > single port RAM
> > and RAM which can be written in one port and read from the other port.
> >
> > How shall I solve this problem?
> >
> > Thank you.

>
> You might get a better idea of the particulars by looking at a data
> sheet for IDT dual-port memories. (www.idt.com)



[email protected] 03-02-2006 09:13 AM

Re: How do I make dual-port RAM from single port RAM?
 
Senior Library Design Engineer (NEW) The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.
5+ years industrial experience designing CMOS VLSI standard cell
libraries.
Full understanding of the ASIC design flow and the role of standard
cell libraries.
Experienced in full custom design and layout.
Knowledge of the cell characterization process.
Basic understanding of silicon processing technology.
Understanding of place and route tools, and how they work.
Comfortable with the Linix operating system and strong programming
skills in perl.
Experience working with silicon foundries, preferably TSMC.
Full understanding of the following IC Design tools:
HSPICE
Verilog logic simulation
Cadence Composer
Cadence Virtuoso
Synopsys Design Compiler
A proven track record of successful design projects - completed on
schedule.
Excellent communication skills.
Leadership skills and a personal commitment to the team's success are
also required attributes
Junior Library Design Engineer (NEW) The candidate should possess a
BSEE degree (MSEE preferred) with emphasis in VLSI circuit design.
3+ years industrial experience designing CMOS digital circuits.
Understanding of circuit simulation with SPICE.
Experienced with physical design rules and IC layout.
Knowledge of the Cadence design tools.
Some experience with Verilog modeling and synthesis tools.
Good computer skills and moderate programming experience with perl.
Strong team member with positive learning attitude.
Good oral and written communication skills.
What we expect from you:
If you find this opening interesting then kindly forward your profile
in word format along with your current CTC & expected CTC details to
[email protected] ASAP. Kindly inform the same to your
colleagues and friends.



Thanks & Regards,

Komal Tripathi.

____________________________

PriorityONE Consulting

Your Success is our PRIORITY # 1!

Contact me:

India Mobile: +91-9945341452.

Direct Lines: 080-41313872

E-mail: [email protected]



PriorityONE Consulting provides the best technical talent to suit the
needs of

high end software companies for the entire technology and hierarchy
spectrum.

We serve our clients and our candidates with respect and commitment.


Josep Durán 03-02-2006 09:48 AM

Re: How do I make dual-port RAM from single port RAM?
 

"Ulf Samuelsson" <[email protected]> escribió en el mensaje
news:[email protected]
>
>
> You can instantiate FOUR rams and implement a valid bit for each location
> in a register.
> PortA can write to RAM0,RAM1 and read from RAM0 and RAM2
> PortB can write to RAM2,RAM3 and read from RAM1 and RAM3
>
> When PortA writes to address position 17, both RAM0[17] and RAM1[17] are
> updated and the
> VALID_BIT[17] is set to 0 indicating that RAM0,1 are valid instead of
> RAM2,3.
>
> When PortB reads address position 17, both RAM1 and RAM3 are read.
> A multiplexer on the output is controlled by the selected VALID_BIT,
> and since VALID_BIT[17] is zero, it will select the output of RAM1 over
> RAM3.
>
> Obviously this is going to use some gates,so it is not practical for large
> SRAMs.
> Running the RAM at 2 x frequency is going to cost a lot less.
>
>


Following the previous example, I fail to see how can I read PortB address
17
(last time written through portA) while PortA is writing adddress (say) 22.

Am I missing something ?



Regards

Josep Duran




John_H 03-02-2006 04:48 PM

Re: How do I make dual-port RAM from single port RAM?
 
Use 2 1Wr2Rd RAMs that are in your library.

Rather than writing a value to both RAMs, write the XOR of the read
value from the other RAM with the write data. To read the valid data,
read the value in both RAMs and XOR them. The read XOR will provide
the last data written to that location. This gets you most of the way.

If you have a write to both ports at the same address - invalid in some
dual-port memories - collision arbitration needs to decide who gets the
write; the winning RAM writes, the losing RAM doesn't. If both RAMs
write in a collision, the data is invalid.

If you guarantee that two writes to the same location never occur at
the same time, the only constraint is that writes to the same address
are never too close (write data becomes valid for read in RAM1 before
RAM2 uses the read data to update that address in RAM2).

This should give you 100% dual-port RAM without too much trouble. You
then only need to worry about the 1Wr2Rd RAM behavior as far as async
vs sync read-first versus sync write-first.

Yay?


rhnlogic 03-03-2006 02:24 AM

Re: How do I make dual-port RAM from single port RAM?
 
Frank @ CN wrote:
> In my application, a RAM needs to be written/read from two sets of
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some
> single port RAM
> and RAM which can be written in one port and read from the other port.
>
> How shall I solve this problem?


If you have a faster clock available, one common way to solve
this kind of problem is to time-division multiplex the 1-ported RAM.
Essentially run two (or more) successive memory read/write
cycles one the ASIC, per one read/write time slot on the FPGA.

You can also use this technique inside an FPGA to make the
fast dual-port RAMs look like 4 or more ported, but slower,
memories.


IMHO. YMMV.
--
rhn A.T nicholson d.0.t C-o-M


Derek Simmons 03-03-2006 07:10 PM

Re: How do I make dual-port RAM from single port RAM?
 
I haven't had time to load Xilinx's tools (sometime I'm going to have
to do it for another project) to see what there DPRAM library device
looks like.

The solution I was going to offer was going to be a time division
solution like rhnlogic suggested. Relative to the reading/writing of
the ports of the DPRAM, what clocks are available? What other controls
signals are present that could be taken advantage of?

If you want to reinvent the wheel you could implement your own dual
port memory. It would probably be a little bit more than 6240 flip
flops if you can limit the address to 130 range and if you're sloppy
about it 16384 flip flops for the whole 256 range. (plus addressing and
control support)

Derek


[email protected] 03-05-2006 01:43 AM

Re: How do I make dual-port RAM from single port RAM?
 
When you wrote PortA address 17, you wrote into address 17 of RAM0 and
RAM1. You also wrote 0 (meaning A is valid) into address 17 of
VALID_BIT. When you read PortB address 17, you read address 17 of RAM1
and RAM3. You also read address 17 of VALID_BIT, which gives you back
0, telling you to select the output of RAM1. This gives you the value
you just wrote to RAM1 when you wrote to PortA address 17.

If you had written to address 17 via PortB last, then address 17 of
VALID_BIT would have been set to 1, telling you to select the output of
RAM3 instead. This would have been correct, since a write to portB
would have written to RAM2 and RAM3. If you read portA address 17, you
will read address 17 of RAM0 and RAM2 instead, and selected between
those based on VALID_BIT.

Or perhaps what you are missing is that each of these RAMs has a read
port and a write port, which can be used simultaneously with
independent addresses. This was one of the components that was
described as being available. So PortB can be reading address 17 of
RAM1 at the same time PortA is writing address 22 of RAM1.


[email protected] 03-05-2006 01:58 AM

Re: How do I make dual-port RAM from single port RAM?
 
Another clever solution. This requires the same amount of RAM as Ulf's
scheme, but without requiring the 2Rd/2Wr VALID_BIT array. However, it
may require a longer write cycle time, to allow completing the
associated read and XOR with enough setup time for the write. But part
of the write can overlap the read, so it should still be faster than
the time-multiplexing approaches.


John_H 03-05-2006 02:55 AM

Re: How do I make dual-port RAM from single port RAM?
 
[email protected] wrote:
> Another clever solution. This requires the same amount of RAM as Ulf's
> scheme, but without requiring the 2Rd/2Wr VALID_BIT array. However, it
> may require a longer write cycle time, to allow completing the
> associated read and XOR with enough setup time for the write. But part
> of the write can overlap the read, so it should still be faster than
> the time-multiplexing approaches.


What I did forget is that the memory may be synchronous read and write.
If the read is asynchronous then this method still works but youre
comment on timing is well taken. In the FPGA there's a nice, small
setup time for memory address and data. An asynchronous read would
require the address access time before that XOR. If the translation is
from FPGA to ASIC, there may be enough margin in the timing to specify
the read access and XOR from the address and the XOR alone from the data
before the write strobe.

If the ASIC memory is synchronous read without the async data, this
method would require more RAMs and some feedback to account for
just-written addresses.

Is the memory 1Wr/2Rd memory primitive an asynchronous read?

Josep Durán 03-06-2006 12:33 PM

Re: How do I make dual-port RAM from single port RAM?
 

<[email protected]> escribió en el mensaje
news:[email protected] oups.com...
>
> Or perhaps what you are missing is that each of these RAMs has a read
> port and a write port, which can be used simultaneously with
> independent addresses. This was one of the components that was
> described as being available. So PortB can be reading address 17 of
> RAM1 at the same time PortA is writing address 22 of RAM1.
>



After reading your post I went back to the OP, and it was _clearly_ stated
the availability of such a component.

Thank you for pointing it out.





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