FPGA Central

My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one byte
each clock period. What are the equations to inplement this data scrambler?


Thanks.

Apply it eight times before clocking; the tools will do the rest.

I'm not familiar with exactly the way you wrote your equation, but whatever
you mean by it, apply it eight times to get your "byte" result.

Jason

"Kris Neot" <[email protected]> wrote in message
news:[email protected]...
> My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one byte
> each clock period. What are the equations to inplement this data
> scrambler?
>
>
> Thanks.
>
>
>

Kris Neot wrote:
> My polynomial is S(x) = x(-7) + x(04) + 1, but my input data is one byte
> each clock period. What are the equations to inplement this data scrambler?
>
>
> Thanks.

You may have to create a look-up table (LUT) that contains various "S"
values for different "x" inputs. An LUT is kind of like ROM where you
would use your "x" input as the address. These "S" values are easily
computed using Excel or an open-source equivalent spreadsheet program.

Also the previous suggestion of performing a multiplication operation
several times per cycle is a pretty good idea but it eats up resources
or time:
m = 1/x
n = m * m * m * m * m * m * m
o = x * x * x * x
S(x) = n + o + 1

"m" will use up multiplication logic (to create the divider)
"n" will use up the logic needed for 7 multipliers. *OR* If you adjust
your data so that "n" is 8 bits wide then you can use a single
multiplier that is 56-bits wide (7*8) but it will take 7 cycles to
complete the operation.

I recommend using the LUT technique.

Best Regards
-Derek

And, you can check your result against the web-tool output at

http://www.easics.com/webtools/crctool

Very neat, thank you Charles.




"Charles Gardiner" <[email protected]> wrote in message
news:[email protected]...
> And, you can check your result against the web-tool output at
>
> http://www.easics.com/webtools/crctool
>
>