FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 06-21-2007, 05:14 AM
samuel
Guest
 
Posts: n/a
Default How to bind multiple sva modules(spec) with one verilog modules(dut)?

Hi,

I have a verilog module (dut) composed of several different bus
interfaces , and I have the corresponding bus sva vip module for each
bus i/f. So I need bind them to the verilog module.

Does anyone know how to bind ?


Thanks in advance,

Samuel

Reply With Quote
  #2 (permalink)  
Old 06-21-2007, 09:24 AM
Guest
 
Posts: n/a
Default Re: How to bind multiple sva modules(spec) with one verilog modules(dut)?

On Jun 21, 8:14 am, samuel <[email protected]> wrote:
> Hi,
>
> I have a verilog module (dut) composed of several different bus
> interfaces , and I have the corresponding bus sva vip module for each
> bus i/f. So I need bind them to the verilog module.
>
> Does anyone know how to bind ?
>
> Thanks in advance,
>
> Samuel


try
bind <name of the module in which to bind>: <name of the instances in
which the to bind> <name of the module to be instantiated or bound>
<name of the instantation>( port map )

like

bind parag: p1,p2,p3 samuel s1(a,b,c);


where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
inside parag
-Parag

Reply With Quote
  #3 (permalink)  
Old 06-22-2007, 05:48 AM
samuel
Guest
 
Posts: n/a
Default Re: How to bind multiple sva modules(spec) with one verilog modules(dut)?

On Jun 21, 3:24 pm, "[email protected]" <[email protected]>
wrote:
> On Jun 21, 8:14 am, samuel <[email protected]> wrote:
>
> > Hi,

>
> > I have a verilog module (dut) composed of several different bus
> > interfaces , and I have the corresponding bus sva vip module for each
> > bus i/f. So I need bind them to the verilog module.

>
> > Does anyone know how to bind ?

>
> > Thanks in advance,

>
> > Samuel

>
> try
> bind <name of the module in which to bind>: <name of the instances in
> which the to bind> <name of the module to be instantiated or bound>
> <name of the instantation>( port map )
>
> like
>
> bind parag: p1,p2,p3 samuel s1(a,b,c);
>
> where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
> inside parag
> -Parag



So here p1,p2,p3 is the vip module and samuel is the dut module ?

Rgds,

S.

Reply With Quote
  #4 (permalink)  
Old 06-22-2007, 05:52 AM
samuel
Guest
 
Posts: n/a
Default Re: How to bind multiple sva modules(spec) with one verilog modules(dut)?

On Jun 21, 3:24 pm, "[email protected]" <[email protected]>
wrote:
> On Jun 21, 8:14 am, samuel <[email protected]> wrote:
>
> > Hi,

>
> > I have a verilog module (dut) composed of several different bus
> > interfaces , and I have the corresponding bus sva vip module for each
> > bus i/f. So I need bind them to the verilog module.

>
> > Does anyone know how to bind ?

>
> > Thanks in advance,

>
> > Samuel

>
> try
> bind <name of the module in which to bind>: <name of the instances in
> which the to bind> <name of the module to be instantiated or bound>
> <name of the instantation>( port map )
>
> like
>
> bind parag: p1,p2,p3 samuel s1(a,b,c);
>
> where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
> inside parag
> -Parag


So p1,p2,p3 are sva vips and samuel is the verilog dut module ,
right ?

Rgds,

S.


Reply With Quote
  #5 (permalink)  
Old 06-22-2007, 07:12 AM
Guest
 
Posts: n/a
Default Re: How to bind multiple sva modules(spec) with one verilog modules(dut)?

On Jun 22, 8:48 am, samuel <[email protected]> wrote:
> On Jun 21, 3:24 pm, "[email protected]" <[email protected]>
> wrote:
>
>
>
> > On Jun 21, 8:14 am, samuel <[email protected]> wrote:

>
> > > Hi,

>
> > > I have a verilog module (dut) composed of several different bus
> > > interfaces , and I have the corresponding bus sva vip module for each
> > > bus i/f. So I need bind them to the verilog module.

>
> > > Does anyone know how to bind ?

>
> > > Thanks in advance,

>
> > > Samuel

>
> > try
> > bind <name of the module in which to bind>: <name of the instances in
> > which the to bind> <name of the module to be instantiated or bound>
> > <name of the instantation>( port map )

>
> > like

>
> > bind parag: p1,p2,p3 samuel s1(a,b,c);

>
> > where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
> > inside parag
> > -Parag

>
> So here p1,p2,p3 is the vip module and samuel is the dut module ?
>
> Rgds,
>
> S.


hi Samuel,
Yes ,
YOu will see the following hierarchial names after that
p1.s1
p2.s1
p3.s1

I hope this time I hit the gong

Reply With Quote
  #6 (permalink)  
Old 06-22-2007, 11:38 AM
samuel
Guest
 
Posts: n/a
Default Re: How to bind multiple sva modules(spec) with one verilog modules(dut)?

On Jun 22, 1:12 pm, "[email protected]" <[email protected]>
wrote:
> On Jun 22, 8:48 am, samuel <[email protected]> wrote:
>
>
>
> > On Jun 21, 3:24 pm, "[email protected]" <[email protected]>
> > wrote:

>
> > > On Jun 21, 8:14 am, samuel <[email protected]> wrote:

>
> > > > Hi,

>
> > > > I have a verilog module (dut) composed of several different bus
> > > > interfaces , and I have the corresponding bus sva vip module for each
> > > > bus i/f. So I need bind them to the verilog module.

>
> > > > Does anyone know how to bind ?

>
> > > > Thanks in advance,

>
> > > > Samuel

>
> > > try
> > > bind <name of the module in which to bind>: <name of the instances in
> > > which the to bind> <name of the module to be instantiated or bound>
> > > <name of the instantation>( port map )

>
> > > like

>
> > > bind parag: p1,p2,p3 samuel s1(a,b,c);

>
> > > where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
> > > inside parag
> > > -Parag

>
> > So here p1,p2,p3 is the vip module and samuel is the dut module ?

>
> > Rgds,

>
> > S.

>
> hi Samuel,
> Yes ,
> YOu will see the following hierarchial names after that
> p1.s1
> p2.s1
> p3.s1
>
> I hope this time I hit the gong


Thanks Parag,

But according to the systemverilog 3.1a spec , the module(dut) is
before the constraint/program (vip) when binding.
So ......

Rgds,

Samuel

The spec described below :

bind_directive ::= bind hierarchical_identifier constant_select
bind_instantiation ;
bind_instantiation ::=
program_instantiation
| module_instantiation
| interface_instantiation


Example of binding a program instance to a module:
bind cpu fpu_props fpu_rules_1(a,b,c);
Where:
- cpu is the name of module.
- fpu_props is the name of the program containing properties.
- fpu_rules_1 is the program instance name.
- Ports (a, b,c) get bound to signals (a,b,c) of module cpu.
- Every instance of cpu gets the properties.
Example of binding a program instance to a specific instance of a
module:






Reply With Quote
  #7 (permalink)  
Old 06-22-2007, 03:21 PM
Guest
 
Posts: n/a
Default Re: How to bind multiple sva modules(spec) with one verilog modules(dut)?

That simply means that the property will names

cpu.fpu_rules_1()
isnt it ?
We are both on the same boat but, you on star board and me on the port
side
-Parag


samuel wrote:
> On Jun 22, 1:12 pm, "[email protected]" <[email protected]>
> wrote:
> > On Jun 22, 8:48 am, samuel <[email protected]> wrote:
> >
> >
> >
> > > On Jun 21, 3:24 pm, "[email protected]" <[email protected]>
> > > wrote:

> >
> > > > On Jun 21, 8:14 am, samuel <[email protected]> wrote:

> >
> > > > > Hi,

> >
> > > > > I have a verilog module (dut) composed of several different bus
> > > > > interfaces , and I have the corresponding bus sva vip module for each
> > > > > bus i/f. So I need bind them to the verilog module.

> >
> > > > > Does anyone know how to bind ?

> >
> > > > > Thanks in advance,

> >
> > > > > Samuel

> >
> > > > try
> > > > bind <name of the module in which to bind>: <name of the instances in
> > > > which the to bind> <name of the module to be instantiated or bound>
> > > > <name of the instantation>( port map )

> >
> > > > like

> >
> > > > bind parag: p1,p2,p3 samuel s1(a,b,c);

> >
> > > > where p1,p2 and p3 will have a mod instance s1 bound with a,b,c all
> > > > inside parag
> > > > -Parag

> >
> > > So here p1,p2,p3 is the vip module and samuel is the dut module ?

> >
> > > Rgds,

> >
> > > S.

> >
> > hi Samuel,
> > Yes ,
> > YOu will see the following hierarchial names after that
> > p1.s1
> > p2.s1
> > p3.s1
> >
> > I hope this time I hit the gong

>
> Thanks Parag,
>
> But according to the systemverilog 3.1a spec , the module(dut) is
> before the constraint/program (vip) when binding.
> So ......
>
> Rgds,
>
> Samuel
>
> The spec described below :
>
> bind_directive ::= bind hierarchical_identifier constant_select
> bind_instantiation ;
> bind_instantiation ::=
> program_instantiation
> | module_instantiation
> | interface_instantiation
>
>
> Example of binding a program instance to a module:
> bind cpu fpu_props fpu_rules_1(a,b,c);
> Where:
> - cpu is the name of module.
> - fpu_props is the name of the program containing properties.
> - fpu_rules_1 is the program instance name.
> - Ports (a, b,c) get bound to signals (a,b,c) of module cpu.
> - Every instance of cpu gets the properties.
> Example of binding a program instance to a specific instance of a
> module:


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Number of Modules in a Verilog File [email protected] Verilog 1 08-30-2006 08:39 PM
sub modules mmt1 Verilog 3 08-22-2006 05:23 PM
Synthesis Quesiton (single module vs. multiple modules) thomasc Verilog 2 03-10-2005 08:51 AM
How to Include Multiple modules in One Large Module Sridhar_Gadda Verilog 1 02-23-2005 07:58 PM
2 modules pat Verilog 1 09-08-2004 05:35 PM


All times are GMT +1. The time now is 08:10 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved