Re: How to avoid pulse swallowing?
Distributed delays (i.e. the delays on continuous assignments or gate
primitives) are always inertial in Verilog.
Non-blocking assignments provide "pure transport" delays. This may
give you what you need for your purposes. However, unlike VHDL
transport delays, they won't swallow pulses even if the effective pulse
width goes negative. In other words, if you schedule the leading edge
of a pulse, and then schedule the trailing edge to happen before the
leading edge, you will get the trailing edge value and then the leading
edge value. However, as long as you are only using a single
propagation delay, this won't be a problem.
Verilog also provides path delays from port to port, using "specify"
blocks. With these, you can control the pulse-filtering behavior. The
default is 100% filtering, which is equivalent to inertial delay. If
you set it to 0% filtering, you will get transport delay. Or you can
set it to something in between, to filter pulses with widths up to a
given percentage of the propagation delay. However, I wouldn't
recommend trying to learn about Verilog's more advanced timing features
unless you are prepared for a lot of extra effort.
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