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Old 07-02-2009, 07:24 PM
Veeresh
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Default Have question regarding parameter usage in verilog

Hi all,

I am new to systemverilog and I have to write synthesizable .sv. I
have some peculiar requirement and I have thought of following pseudo
code for my requirement.

My requirement: parametrized number of registers and bit widths in
each registers. Following shows an example

reg1 [0:13]
reg2 [0:3]
..
..
..
..
..
..
reg100 [0-34]

==================================================
code
==================================================
module top ();
parameter no_of_regs = 100;
paramerer register1_width = 13;
paramerer register2_width = 3;
paramerer register3_width = 103;
paramerer register4_width = 32;
..
..
..
..
..
paramerer register100_width = 34;


genvar i,j;
for i (0 to no_of_regs)
for j (0 to register1_width)
dff DFF[no_of_regs] #(register1_width) (.clk(clk), .in(in
[register1_width]), .en(en[i]), .out(out[register1_width]));
endfor
endfor
endmodule


module dff #(parameter register_width = 1)(clk, in, en, out);
endmodule
==================================================

My understanding with this code.
i generates 100 registers.
Instance name is DFF[0], DFF[1], DFF[2]......DFF[100]
If I want to access particular instance, I can use DFF[0], DFF[1], DFF
[2]......DFF[100]
Also en is array of lengh 100, en[0], en[1], en[2].....en[100]

I was unable to find following from the spec.

Line for j (0 to register1_width) - this line will generate only one
register.
How to vary register width for each value of i?

Also, if I declare parameters as given below.

paramerer register[0] = 13;
paramerer register[1] = 3;
paramerer register[2] = 103;
paramerer register[3] = 32;
..
..
..
..
..
paramerer register[100] = 34;

Can I use following generate statement?
genvar i,j;
for i (0 to no_of_regs)
for j (0 to register[i])
dff DFF[no_of_regs] (.clk(clk), .in(in[register[j]), .en(en
[j]), .out(out[register[j]]));
endfor
endfor
endmodule

Please help me.

Thanks,
Veeresh
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  #2 (permalink)  
Old 07-03-2009, 09:53 PM
Jonathan Bromley
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Default Re: Have question regarding parameter usage in verilog

On Thu, 2 Jul 2009 11:24:38 -0700 (PDT), Veeresh wrote:

>My requirement: parametrized number of registers and
>bit widths in each registers.


Your sample code had many syntax errors, and was
unnecessarily verbose, but you definitely have the
right idea.

How about this example? It uses SystemVerilog's
ability to have parameters of any data type,
together with the assignment-pattern syntax
for writing array values. The parameter, as
you suggested, is an array of integers representing
the various registers' sizes. A generate loop
constructs the various registers.

module jagged_regs;
parameter num_regs = 8;
parameter int reg_sizes[num_regs] =
'{2, 4, 6, 3, 5, 5, 3, 9};
generate
genvar i;
for (i=0; i<num_regs; i++) begin
reg [reg_sizes[i]-1:0] R;
end
endgenerate
endmodule

This works today in two out of three major
simulators - a third has not yet implemented
unpacked-array parameters. However, there are
some tricky issues about overriding the
parameters - I made that work in both
simulators, but I needed a different coding
style for each.

For synthesis, I found two FPGA-oriented synthesis
tools that accept it. If this is important to you,
and your chosen tool vendors don't yet support it,
it would be very reasonable for you to file
enhancement requests with them; there is nothing
crazy about what you're trying to do.

I'm intrigued to know what you intend to do
with those varying-size registers, though.
I can imagine the remainder of the code
becoming quite "interesting"....
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

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  #3 (permalink)  
Old 07-09-2009, 05:47 PM
Veeresh
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Posts: n/a
Default Re: Have question regarding parameter usage in verilog

On Jul 4, 1:53*am, Jonathan Bromley <[email protected]>
wrote:
> On Thu, 2 Jul 2009 11:24:38 -0700 (PDT), Veeresh wrote:
> >My requirement: parametrized number of registers and
> >bit widths in each registers.

>
> Your sample code had many syntax errors, and was
> unnecessarily verbose, but you definitely have the
> right idea.
>
> How about this example? *It uses SystemVerilog's
> ability to have parameters of any data type,
> together with the assignment-pattern syntax
> for writing array values. *The parameter, as
> you suggested, is an array of integers representing
> the various registers' sizes. *A generate loop
> constructs the various registers.
>
> module jagged_regs;
> * parameter num_regs = 8;
> * parameter int reg_sizes[num_regs] =
> * * '{2, 4, 6, 3, 5, 5, 3, 9};
> * generate
> * * genvar i;
> * * for (i=0; i<num_regs; i++) begin
> * * * reg [reg_sizes[i]-1:0] R;
> * * end
> * endgenerate
> endmodule
>
> This works today in two out of three major
> simulators - a third has not yet implemented
> unpacked-array parameters. However, there are
> some tricky issues about overriding the
> parameters - I made that work in both
> simulators, but I needed a different coding
> style for each.
>
> For synthesis, I found two FPGA-oriented synthesis
> tools that accept it. *If this is important to you,
> and your chosen tool vendors don't yet support it,
> it would be very reasonable for you to file
> enhancement requests with them; there is nothing
> crazy about what you're trying to do.
>
> I'm intrigued to know what you intend to do
> with those varying-size registers, though.
> I can imagine the remainder of the code
> becoming quite "interesting"....
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> [email protected]://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Thanks Jonathan.
I tried your style and seems like simulator is not happy.
Let me try again sometime later. But, I followed other way of
implementatation.

module jagged_regs;
parameter num_regs = 8;
parameter int [3:0] [num_reg-1:0] reg_sizes = {2, 4, 6, 3, 5, 5, 3,
9};
generate
genvar i;
for (i=0; i<num_regs; i++) begin
reg [reg_sizes[i*4+3:i*4]:0] R;
end
endgenerate
endmodule

NOTE: Code is not exactly same but I would like to show the concept
and it worked. I haven't tried synthesis yet.

This kind of requirement is necessary only when IPs are used by many
groups and they implement their own registers.
In my case, basic functionality remains same but registers definition
varies. So, I have to write common code (block) and scalable register
set.

Thanks for your help again.

Regards,
Veeresh
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