FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-03-2004, 05:04 PM
Steve Meyer
Guest
 
Posts: n/a
Default GPL Cver now supports Cygwin

We just uploaded GPL Cver 1.10g with support for Windows using
Cygwin to www.pragmatic-c.com/gpl-cver site. There is now a makefile for
Cygwin and PLI works with Cygwin release 1.55 and earlier. Parameter code
has been rewritten to match XL for both pound and defparams. Hopefully,
this answers the posts that were critical of GPL Cver.

Also, we think Cver is comparable in speed to XL for realistic designs.
It can be slower for designs that do not use SDF and path delays and timing
checks because Cver does not flatten designs. This is reason Cver requires
much less memory than other simulators at the cost that simulation when
there are few scheduled events is slower.

We are working on speed improvements and would appreciate bug reports
if you can send us the Verilog source for designs that you think are
particularly slow.
/Steve



--
Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email: [email protected]
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
verilator on cygwin pini Verilog 0 01-21-2004 11:34 AM


All times are GMT +1. The time now is 06:36 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved