FPGA Central

Hi,

I need to generate a 70MHz clock from 210MHz. Is there any way to
generate it rather than using a DCM.

Thanks,

Sudheer

This is not a hard problem if you don't care about duty cycle. I'll
leave that for you to logic out, but if you need 50% duty cycle then
there are tricks.

Peter Alfke from Xilinx wrote an excellent article about clock dividers
titled "Unusual Clock Dividers." It was published the Xilinx's Xcell
Journal. I believe issue 33, but it appears Xilinx has gotten rid of
that article as it's archives don't go back far at all anymore.

You could probably find it through some googling, but this brings up
another point: Why would Xilinx remove it's archives? It's not like
the material was dated.

That particular article has been of use to me several times. Peter
wrote a great article. I'd like to see it come back.

-Arlen


K. Sudheer Kumar wrote:
> Hi,
>
> I need to generate a 70MHz clock from 210MHz. Is there any way to
> generate it rather than using a DCM.
>
> Thanks,
>
> Sudheer

module clock_div3
(
clock_in,
clock_out
);

input clock_in;
output clock_out;

reg clock_out;
reg [2:1] d_pos;
reg [2:1] d_neg;


always @ (posedge clock_in)
case (d_pos)
2'b00: d_pos[2:1] <= 2'b01;
2'b01: d_pos[2:1] <= 2'b11;
default: d_pos[2:1] <= 2'b00;
endcase

always @ (negedge clock_in)
case (d_neg)
2'b00: if (d_pos[1]) d_neg[2:1] <= 2'b01;
2'b01: d_neg[2:1] <= 2'b10;
default: d_neg[2:1] <= 2'b00;
endcase

always @ (posedge clock_in or posedge (d_neg[1] & !clock_in))
if (d_neg[1] & !clock_in)
clock_out <= 1'b0;
else
if (!d_pos[1]) clock_out <= 1'b1;

endmodule

K. Sudheer Kumar schrieb:

> I need to generate a 70MHz clock from 210MHz. Is there any way to
> generate it rather than using a DCM.

You could use pseudo dual-edge flipflops.
http://www.ralf-hildebrandt.de/publi...ff/pde_dff.pdf

Ralf