FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-14-2006, 04:17 PM
Davy
Guest
 
Posts: n/a
Default General Tips of reading Verilog Code

Hi all,

Is there any general tips of reading Verilog code. I want to collect
these tips to accelerate code reading speed.

For example, shall I read the input signal first and trace them until
output?
And shall I read from top to bottom or from bottom to top?
And shall I read the 'always' block first?

Any questions and comments are welcome

Best regards,
Davy

Reply With Quote
  #2 (permalink)  
Old 09-14-2006, 07:36 PM
Jonathan Bromley
Guest
 
Posts: n/a
Default Re: General Tips of reading Verilog Code

On 14 Sep 2006 07:17:49 -0700, "Davy" <[email protected]> wrote:

>Hi all,
>
>Is there any general tips of reading Verilog code. I want to collect
>these tips to accelerate code reading speed.
>
>For example, shall I read the input signal first and trace them until
>output?
>And shall I read from top to bottom or from bottom to top?
>And shall I read the 'always' block first?


Personally, I like to read the comments first.
Sadly, that often doesn't take very long :-)
So then I start by looking at port lists, and trying to
identify standard interface protocols on the ports.
Then I usually find it's easiest to look at the "always"
procedural code, but that's not a lot of help when people
write Verilog as if it was just another way of describing a
schematic; in those cases I confess that I usually try to
sketch out a schematic showing interconnection between
the various always blocks and continuous assignments.
By this stage I probably have a fairly good idea what's
going on, have already consumed rather a lot of coffee,
and am getting very angry with the author for his failure
(it always is 'his', I suspect that female Verilog coders
probably document better than male) to document anything.

Once I've got to the stage where I understand what
each DECLARATION is there for, I probably know all
I need to know.

Running a sim can help a lot, too.

Occasionally, if you're very lucky, you get some
supporting documentation. Read it, several times,
before starting work on the code.

Verification code is even harder to follow unless it
has been nicely written and well commented, because
procedural calls from one module into another are
often far from obvious at a glance.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Reply With Quote
  #3 (permalink)  
Old 09-15-2006, 03:02 PM
Jim Wu
Guest
 
Posts: n/a
Default Re: General Tips of reading Verilog Code

I think the best way to understand a piece of code it's to run
simulation on it and check the waveforms. Also a good simulator with
shematic view of the source code will be helpful.

HTH,
Jim
http://home.comcast.net/~jimwu88/tools/

Davy wrote:
> Hi all,
>
> Is there any general tips of reading Verilog code. I want to collect
> these tips to accelerate code reading speed.
>
> For example, shall I read the input signal first and trace them until
> output?
> And shall I read from top to bottom or from bottom to top?
> And shall I read the 'always' block first?
>
> Any questions and comments are welcome
>
> Best regards,
> Davy


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Reading synopsys .lib into BuildGates Rohit Verilog 1 03-31-2006 02:05 PM
Learning SystemVerilog in General [email protected] Verilog 1 09-27-2005 05:12 PM
verilog code reading problem anupam Verilog 2 09-15-2004 03:39 PM
How to be some "General Purpose" style? SnailMan Verilog 1 08-07-2004 07:57 PM
Verilog Netlest Reader Code, ATPG Code Robert Posey Verilog 0 11-20-2003 12:41 AM


All times are GMT +1. The time now is 06:22 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved