FPGA Central

Greetings,

I have a 4-bit chip select bus (1 of 16) that I want to use as an
event. The simplest solution is to simply AND the 4 input lines to
produce a single signal called ChipSelect. As you probably know using
this signal in an 'always' block returns the 'Gated clock' warning.
Is there a solution to this problem?

Thanks

Chip wrote:

> I have a 4-bit chip select bus (1 of 16) that I want to use as an
> event. The simplest solution is to simply AND the 4 input lines to
> produce a single signal called ChipSelect. As you probably know using
> this signal in an 'always' block returns the 'Gated clock' warning.
> Is there a solution to this problem?

A clocked block that ChipSelect as an input.

-- Mike Treseler

On Jul 15, 10:37*pm, Chip <[email protected]> wrote:
> Greetings,
>
> I have a 4-bit chip select bus (1 of 16) that I want to use as an
> event. *The simplest solution is to simply AND the 4 input lines to
> produce a single signal called ChipSelect. *As you probably know using
> this signal in an 'always' block returns the 'Gated clock' warning.
> Is there a solution to this problem?
>
> Thanks

if you wanna use it as asynchronous event then yes, is it critical for
you?
if not just use it as conditional statement, in other words

always @ (posedge xClk)begin
if (!CS) begin
............
............
............


end
end

On Jul 15, 9:42*pm, rubson <[email protected]> wrote:
> On Jul 15, 10:37*pm, Chip <[email protected]> wrote:
>
> > Greetings,
>
> > I have a 4-bit chip select bus (1 of 16) that I want to use as an
> > event. *The simplest solution is to simply AND the 4 input lines to
> > produce a single signal called ChipSelect. *As you probably know using
> > this signal in an 'always' block returns the 'Gated clock' warning.
> > Is there a solution to this problem?
>
> > Thanks
>
> if you wanna use it as asynchronous event then yes, is it critical for
> you?
> if not just use it as conditional statement, in other words
>
> always @ (posedge xClk)begin
> if (!CS) begin
> ............
> ............
> ............
>
> end
> end

This is a SPI slave engine. I want to build a state machine that
responds to each bit communicated via SPI. This requires that I know
the count/index of each bit. I want the /CS event to clear the bit
count/index back to 0 BEFORE the SPI clock edges begin to clock in
data.

If CS was a single line it would be easy and I could write something
like (in this example SPCK idle polarity is LO):

always @ (negedge CS or posedge SPCK) begin
if(!SPCK)
BitIndex <= 0;
else
BitIndex <= BitIndex + 1;
end

This process initializes the BitIndex at the beginning of each
transfer.

The problem is that I have a 4-bit (1 of 16) CS bus and the only way I
know of to get the equivalent falling edge is to AND the 4 bits:

wire CS;
and(CS, IN[0], IN[1], IN[2], IN[3]);

In this way I get the Gate Clock warning on signal CS.

Any ideas?

Thanks

Chip wrote:

> This is a SPI slave engine.
> Any ideas?

http://www.fpga4fun.com/SPI.html

I think, the reason why you geting warrning of gated clock is not your
and logic CS, it is because you using that CS as a Clock , in your
example you using posedge clock then you using !SCLK as an event,
which will sampled with the negedge Chip Select.
1. Don't warry to much about gated clock warning, ( I guess you are
using Altera CPLD/FPGA, I have done a project with gated clock
warning , and it is still working fine)
2. As I understand you need just a counter which is counting your SPI
input DATA bits, then it shoud reset when SPI access is finished, if
this is rigth then you don't need the CS as an event of always block

parameter BIT;

reg [BIT:0] index;

always @ ( posedge SCLK ) begin
if (!CS)
index <= index +1;
else
index <= 'b0;
end

the index will remain always 0 until the next /CS will fall down:

On Jul 16, 5:47*pm, rubson <[email protected]> wrote:
> I think, the reason why you geting warrning of gated clock is not your
> and logic CS, it is because you using that CS as a Clock , in your
> example you using posedge clock then you using !SCLK as an event,
> which will sampled with the negedge Chip Select.
> 1. Don't warry to much about gated clock warning, ( I guess you are
> using Altera CPLD/FPGA, I have done a project with gated clock
> warning , and it is still working fine)
> 2. As I understand you need just a counter which is counting your SPI
> input DATA bits, then it shoud reset when SPI access is finished, if
> this is rigth then you don't need the CS as an event of always block
>
> parameter BIT;
>
> reg *[BIT:0] index;
>
> always @ ( posedge SCLK ) begin
> * if (!CS)
> * * * * * *index <= index +1;
> * else
> * * * * * *index <= *'b0;
> end
>
> the index will remain always 0 until the next /CS will fall down:

Thanks for the suggestion but the problem is that SCLK only clocks
when CS is LO. In other words the 'else' (reset) will never execute.

Chip wrote:

> Thanks for the suggestion but the problem is that SCLK only clocks
> when CS is LO. In other words the 'else' (reset) will never execute.

CS goes HI when a different slave is accessed.
Consider reading the link I posted.
It explains the interface and implements it in verilog.

-- Mike Treseler

On Jul 17, 9:44*am, Mike Treseler <[email protected]> wrote:
> Chip wrote:
> > Thanks for the suggestion but the problem is that SCLK only clocks
> > when CS is LO. *In other words the 'else' (reset) will never execute.
>
> CS goes HI when a different slave is accessed.
> Consider reading the link I posted.
> It explains the interface and implements it in verilog.
>
> * * * * -- Mike Treseler

I did review your link but that example requires an additional 'clk'
that is faster than SPCK which I don't have.

Thanks anyway

Chip wrote:

> I did review your link but that example requires an additional 'clk'
> that is faster than SPCK which I don't have.

No, that is the SPCK from the master.
It's just a shift register.
Data changes on one edge, but not the other.

see slide 9 here for a better waveform graphic:
http://ww1.microchip.com/downloads/en/devicedoc/spi.pdf