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  #1 (permalink)  
Old 04-03-2007, 01:20 AM
Verictor
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Posts: n/a
Default gate level simulation problem

Hi,

I have a strange problem: the RTL modle simulation looks just fine and
there is no error or warning during synthesis. However, when I use the
gate level netlist to run the same testbench as the RTL simulation,
the results are very different. It looks like the outputs are locked
to all reset values during gate level simulation. I then check the
gate level netlist, no obvious tied nets.

The way I run RTL simulation is like this:

ncverilog model_tb.v model.v

The way I run gate level simulation is like thismodel.net.v is the
netlist file)

ncverilog model_tb.v model.net.v

I guess there is something wrong with the way I run it, not from the
netlist itself. Anyone has similar experience on this?

Thanks.

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  #2 (permalink)  
Old 04-03-2007, 03:51 PM
Ajeetha (www.noveldv.com)
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Posts: n/a
Default Re: gate level simulation problem

On Apr 3, 5:20 am, "Verictor" <[email protected]> wrote:
> Hi,
>
> I have a strange problem: the RTL modle simulation looks just fine and
> there is no error or warning during synthesis. However, when I use the
> gate level netlist to run the same testbench as the RTL simulation,
> the results are very different. It looks like the outputs are locked
> to all reset values during gate level simulation. I then check the
> gate level netlist, no obvious tied nets.
>
> The way I run RTL simulation is like this:
>
> ncverilog model_tb.v model.v
>
> The way I run gate level simulation is like thismodel.net.v is the
> netlist file)
>
> ncverilog model_tb.v model.net.v
>
> I guess there is something wrong with the way I run it, not from the
> netlist itself. Anyone has similar experience on this?
>
> Thanks.


If I may ask you, is this one of your first GLS (Gate Level Sim)
trials? These are sort of issues that tend to appear in early days of
GLS. Some of the common issues include (but not limited to for sure)

1. Clock not toggling
2. Derived clocks/PLLs not getting locked
3. Timescale incorrect
4. Wrong delay_mode usage, try delay_mode_unit
5. If you have SDF, remove it, get first GLS up without SDF then add
SDF.

This is best done on a "trial-and-error" debug phase than via posts.
Talk to a simulation expert.

If you are based in Bangalore, maybe my team can help - but no
commitments (just) yet :-)

Regards
Ajeetha, CVC
www.noveldv.com

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  #3 (permalink)  
Old 04-03-2007, 03:59 PM
Verictor
Guest
 
Posts: n/a
Default Re: gate level simulation problem

On Apr 3, 8:51 am, "Ajeetha (www.noveldv.com)" <[email protected]>
wrote:
> On Apr 3, 5:20 am, "Verictor" <[email protected]> wrote:
>
>
>
>
>
> > Hi,

>
> > I have a strange problem: the RTL modle simulation looks just fine and
> > there is no error or warning during synthesis. However, when I use the
> > gate level netlist to run the same testbench as the RTL simulation,
> > the results are very different. It looks like the outputs are locked
> > to all reset values during gate level simulation. I then check the
> > gate level netlist, no obvious tied nets.

>
> > The way I run RTL simulation is like this:

>
> > ncverilog model_tb.v model.v

>
> > The way I run gate level simulation is like thismodel.net.v is the
> > netlist file)

>
> > ncverilog model_tb.v model.net.v

>
> > I guess there is something wrong with the way I run it, not from the
> > netlist itself. Anyone has similar experience on this?

>
> > Thanks.

>
> If I may ask you, is this one of your first GLS (Gate Level Sim)
> trials? These are sort of issues that tend to appear in early days of
> GLS. Some of the common issues include (but not limited to for sure)
>
> 1. Clock not toggling
> 2. Derived clocks/PLLs not getting locked
> 3. Timescale incorrect
> 4. Wrong delay_mode usage, try delay_mode_unit
> 5. If you have SDF, remove it, get first GLS up without SDF then add
> SDF.
>
> This is best done on a "trial-and-error" debug phase than via posts.
> Talk to a simulation expert.
>
> If you are based in Bangalore, maybe my team can help - but no
> commitments (just) yet :-)
>
> Regards
> Ajeetha, CVCwww.noveldv.com- Hide quoted text -
>
> - Show quoted text -


The problem is actually a setup/hold time issue. I verified that the
rising edge of the clock and data at registers happen to be at the
same time. There is no problem on RTL sim but for gate level netlist.

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  #4 (permalink)  
Old 04-08-2007, 10:02 AM
Guest
 
Posts: n/a
Default Re: gate level simulation problem

On Apr 3, 7:59 pm, "Verictor" <[email protected]> wrote:
> On Apr 3, 8:51 am, "Ajeetha (www.noveldv.com)" <[email protected]>
> wrote:
>
>
>
> > On Apr 3, 5:20 am, "Verictor" <[email protected]> wrote:

>
> > > Hi,

>
> > > I have a strange problem: the RTL modle simulation looks just fine and
> > > there is no error or warning during synthesis. However, when I use the
> > > gate level netlist to run the same testbench as the RTL simulation,
> > > the results are very different. It looks like the outputs are locked
> > > to all reset values during gate level simulation. I then check the
> > > gate level netlist, no obvious tied nets.

>
> > > The way I run RTL simulation is like this:

>
> > > ncverilog model_tb.v model.v

>
> > > The way I run gate level simulation is like thismodel.net.v is the
> > > netlist file)

>
> > > ncverilog model_tb.v model.net.v

>
> > > I guess there is something wrong with the way I run it, not from the
> > > netlist itself. Anyone has similar experience on this?

>
> > > Thanks.

>
> > If I may ask you, is this one of your first GLS (Gate Level Sim)
> > trials? These are sort of issues that tend to appear in early days of
> > GLS. Some of the common issues include (but not limited to for sure)

>
> > 1. Clock not toggling
> > 2. Derived clocks/PLLs not getting locked
> > 3. Timescale incorrect
> > 4. Wrong delay_mode usage, try delay_mode_unit
> > 5. If you have SDF, remove it, get first GLS up without SDF then add
> > SDF.

>
> > This is best done on a "trial-and-error" debug phase than via posts.
> > Talk to a simulation expert.

>
> > If you are based in Bangalore, maybe my team can help - but no
> > commitments (just) yet :-)

>
> > Regards
> > Ajeetha, CVCwww.noveldv.com-Hide quoted text -

>
> > - Show quoted text -

>
> The problem is actually a setup/hold time issue. I verified that the
> rising edge of the clock and data at registers happen to be at the
> same time. There is no problem on RTL sim but for gate level netlist.



Trying disabling timing checks..

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  #5 (permalink)  
Old 04-08-2007, 06:48 PM
Verictor
Guest
 
Posts: n/a
Default Re: gate level simulation problem

On Apr 8, 3:02 am, "[email protected]" <[email protected]> wrote:
> On Apr 3, 7:59 pm, "Verictor" <[email protected]> wrote:
>
>
>
>
>
> > On Apr 3, 8:51 am, "Ajeetha (www.noveldv.com)" <[email protected]>
> > wrote:

>
> > > On Apr 3, 5:20 am, "Verictor" <[email protected]> wrote:

>
> > > > Hi,

>
> > > > I have a strange problem: the RTL modle simulation looks just fine and
> > > > there is no error or warning during synthesis. However, when I use the
> > > > gate level netlist to run the same testbench as the RTL simulation,
> > > > the results are very different. It looks like the outputs are locked
> > > > to all reset values during gate level simulation. I then check the
> > > > gate level netlist, no obvious tied nets.

>
> > > > The way I run RTL simulation is like this:

>
> > > > ncverilog model_tb.v model.v

>
> > > > The way I run gate level simulation is like thismodel.net.v is the
> > > > netlist file)

>
> > > > ncverilog model_tb.v model.net.v

>
> > > > I guess there is something wrong with the way I run it, not from the
> > > > netlist itself. Anyone has similar experience on this?

>
> > > > Thanks.

>
> > > If I may ask you, is this one of your first GLS (Gate Level Sim)
> > > trials? These are sort of issues that tend to appear in early days of
> > > GLS. Some of the common issues include (but not limited to for sure)

>
> > > 1. Clock not toggling
> > > 2. Derived clocks/PLLs not getting locked
> > > 3. Timescale incorrect
> > > 4. Wrong delay_mode usage, try delay_mode_unit
> > > 5. If you have SDF, remove it, get first GLS up without SDF then add
> > > SDF.

>
> > > This is best done on a "trial-and-error" debug phase than via posts.
> > > Talk to a simulation expert.

>
> > > If you are based in Bangalore, maybe my team can help - but no
> > > commitments (just) yet :-)

>
> > > Regards
> > > Ajeetha, CVCwww.noveldv.com-Hidequoted text -

>
> > > - Show quoted text -

>
> > The problem is actually a setup/hold time issue. I verified that the
> > rising edge of the clock and data at registers happen to be at the
> > same time. There is no problem on RTL sim but for gate level netlist.

>
> Trying disabling timing checks..- Hide quoted text -
>
> - Show quoted text -


How to disable timing checks in gate level simulations? I am using NC-
Verilog.

Thanks

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  #6 (permalink)  
Old 04-09-2007, 12:58 AM
Ajeetha (www.noveldv.com)
Guest
 
Posts: n/a
Default Re: gate level simulation problem

On Apr 8, 10:48 pm, "Verictor" <[email protected]> wrote:
> On Apr 8, 3:02 am, "[email protected]" <[email protected]> wrote:
>
> How to disable timing checks in gate level simulations? I am using NC-
> Verilog.
>
> Thanks



In ncelab command, add -notimingchecks as an option.

HTH
Ajeetha, CVC
www.noveldv.com

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