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  #1 (permalink)  
Old 06-25-2003, 07:01 PM
Allen Sun
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Default Fully defined case statement?

Question about case statement, for example:

case (sel)
1'b0: dataout = a;
1'b1: dataout = b;
endcase

Is this fully defined case statement?
How about sel = 'x' or 'z'? Because I know case statement can
distinguish '0', '1', 'x', 'z'.

Thanks.
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  #2 (permalink)  
Old 06-25-2003, 10:38 PM
John_H
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Default Re: Fully defined case statement?

The ca*** or casez construct will distinguish the unknown inputs, requiring
additional entries for the unknowns. Note that the ca*** and casez won't
give you synthesizeable code for the x and z inputs - simulation only. For
simulation, any undefined states should result in an "x" for your output to
make proper sense.

A case should provide unknown outputs for unknown inputs and will not
distinguish the "x" and "z" the way you expect.


"Allen Sun" <[email protected]> wrote in message
news:[email protected] om...
> Question about case statement, for example:
>
> case (sel)
> 1'b0: dataout = a;
> 1'b1: dataout = b;
> endcase
>
> Is this fully defined case statement?
> How about sel = 'x' or 'z'? Because I know case statement can
> distinguish '0', '1', 'x', 'z'.
>
> Thanks.



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  #3 (permalink)  
Old 06-26-2003, 02:51 AM
Rajkumar
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Default Re: Fully defined case statement?

[email protected] (Allen Sun) wrote in message news:<[email protected]ting.google. com>...
> Question about case statement, for example:
>
> case (sel)
> 1'b0: dataout = a;
> 1'b1: dataout = b;
> endcase
>
> Is this fully defined case statement?
> How about sel = 'x' or 'z'? Because I know case statement can
> distinguish '0', '1', 'x', 'z'.
>
> Thanks.


Hi!
The above statement is fully defined.
In real hardware there are only "0" & "1".
And yes there are case statements like ca*** & casez supported in
verilog.
They are used in hardware description if you want to ignore the input.
For e.g. in address decoder
casez(sel)
4'b1??? :
4'b01?? :
4'b00?? :
endcase
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  #4 (permalink)  
Old 06-29-2003, 02:26 AM
Allen Sun
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Posts: n/a
Default Re: Fully defined case statement?

[email protected] (Rajkumar) wrote in message news:<[email protected] com>...
> [email protected] (Allen Sun) wrote in message news:<[email protected] com>...
> > Question about case statement, for example:
> >
> > case (sel)
> > 1'b0: dataout = a;
> > 1'b1: dataout = b;
> > endcase
> >
> > Is this fully defined case statement?
> > How about sel = 'x' or 'z'? Because I know case statement can
> > distinguish '0', '1', 'x', 'z'.
> >
> > Thanks.

>
> Hi!
> The above statement is fully defined.
> In real hardware there are only "0" & "1".
> And yes there are case statements like ca*** & casez supported in
> verilog.
> They are used in hardware description if you want to ignore the input.
> For e.g. in address decoder
> casez(sel)
> 4'b1??? :
> 4'b01?? :
> 4'b00?? :
> endcase


Hi,
Got it, thanks!

Allen
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