FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-25-2003, 09:03 AM
Narendran Kumaraguru Nathan
Guest
 
Posts: n/a
Default editing a vcd file

Hi All,
I use the vcd of my simulation to generate test vectors. Now, I have
a need to edit a vcd file, to change the values of signals at
particular point. I am presently doing that by hand. Does anyone know
about any existing tool to do that?
My actual problem is something like this - assume that reset is
asserted to '0' from time 0 to time 30 ns. Signal "A" was '1' from
time 0 to time 50 ns. Now, I wish to change the value of signal "A" to
'X' during the time when the reset was asserted.... ie. I wish to edit
the vcd file such that signal "A" was 'X' from time 0 to time 30 ns
and value '1' from time 30 ns to 50 ns...
I don't think a simple script will do the job but still I have heard
of some scripts available in perl. Can anybody point me to such
scripts / programs?
I will also like to know wether anyone else also face similar
problems.
Thanks & Regards,
Naren.
Reply With Quote
  #2 (permalink)  
Old 11-25-2003, 08:03 PM
Andy Botterill
Guest
 
Posts: n/a
Default Re: editing a vcd file

In article <[email protected] >, Narendran
Kumaraguru Nathan <[email protected]> writes
>Hi All,
> I use the vcd of my simulation to generate test vectors. Now, I have
>a need to edit a vcd file, to change the values of signals at
>particular point. I am presently doing that by hand. Does anyone know
>about any existing tool to do that?


What is the period of the clock signal?

> My actual problem is something like this - assume that reset is
>asserted to '0' from time 0 to time 30 ns. Signal "A" was '1' from
>time 0 to time 50 ns. Now, I wish to change the value of signal "A" to
>'X' during the time when the reset was asserted.... ie. I wish to edit
>the vcd file such that signal "A" was 'X' from time 0 to time 30 ns
>and value '1' from time 30 ns to 50 ns...


If the number is reasonably small and the timing is simple then ask the
test engineer , *very nicely* , and he may do it for you.

> I don't think a simple script will do the job but still I have heard
>of some scripts available in perl. Can anybody point me to such
>scripts / programs?
> I will also like to know wether anyone else also face similar
>problems.


Devices are often in a strange state until the first instruction has
been decoded. I've seen this before.

>Thanks & Regards,
>Naren.


--
Andy Botterill
Reply With Quote
  #3 (permalink)  
Old 11-26-2003, 05:18 PM
Anthony J Bybell
Guest
 
Posts: n/a
Default Re: editing a vcd file

Andy Botterill <[email protected]> wrote in message news:<[email protected]>...
> In article <[email protected] >, Narendran
> Kumaraguru Nathan <[email protected]> writes
> >Hi All,
> > I use the vcd of my simulation to generate test vectors. Now, I have
> >a need to edit a vcd file, to change the values of signals at
> >particular point. I am presently doing that by hand. Does anyone know
> >about any existing tool to do that?


I can't think of any offhand though surely somebody out there has
written such a thing already.

What I do need to do sometime is come up with a libvcdparse library
such that VCD processing tools will be easy to write. The integrated
approach in gtkwave--while it works--requires siamese twin separation
surgery when wishing to develop other tools from the vcd.c code. Hmm,
I might work on that this weekend as it would greatly simplify the
implementations of the vcd2whatever converters I have laying around.


> > I don't think a simple script will do the job but still I have heard
> >of some scripts available in perl. Can anybody point me to such
> >scripts / programs?
> > I will also like to know wether anyone else also face similar
> >problems.

>
> Devices are often in a strange state until the first instruction has
> been decoded. I've seen this before.


It sounds like you're misunderstanding him...he wants to generate
input stimulus from user-modified VCD files. I've done this before at
work in order to speed up re-simulation of logic fixes. Why sim a
whole processor if you're working on a fix for a bad corner case in
branch predict?

1) run a sim job and generate waves
2) step through the wave file and generate a set of test vectors which
continuously stim all the input ports of your buggy module
3) re-compile the module in question and build a model of just it.
4) stim the module with the values from #2
5) logic fix/repeat at #4 until working

....I forget who, but somebody actually has a patent on this. It
obviously doesn't work on all cases, but can be useful as a quick and
dirty rapid debug solution for logic bugs like missing AND qualifiers
and the like in control logic or whatever. (Note that I usually do
sim the fixed logic on the real model afterwards "just in case".)

-t
Reply With Quote
  #4 (permalink)  
Old 11-27-2003, 07:09 PM
Steve Meyer
Guest
 
Posts: n/a
Default Re: editing a vcd file

On 26 Nov 2003 08:18:25 -0800, Anthony J Bybell <[email protected]> wrote:
> Andy Botterill <[email protected]> wrote in message news:<[email protected]>...
>> In article <[email protected] >, Narendran
>> Kumaraguru Nathan <[email protected]> writes
>> >Hi All,
>> > I use the vcd of my simulation to generate test vectors. Now, I have
>> >a need to edit a vcd file, to change the values of signals at
>> >particular point. I am presently doing that by hand. Does anyone know
>> >about any existing tool to do that?

>
> I can't think of any offhand though surely somebody out there has
> written such a thing already.
>
> What I do need to do sometime is come up with a libvcdparse library
> such that VCD processing tools will be easy to write. The integrated
> approach in gtkwave--while it works--requires siamese twin separation
> surgery when wishing to develop other tools from the vcd.c code. Hmm,
> I might work on that this weekend as it would greatly simplify the
> implementations of the vcd2whatever converters I have laying around.
>
>


gpl cver has a program called vcddiff for 'diffing' two vcd files
that may help in editing your file. It is released under the
GNU free software GPL license so you could also use the VCD file reading code
but it is not separated out as a VCD reading library. If anyone has
ideas for tools or features needed for maniuplating VCD files (that are not
patented), we would add it to the vcddiff part of Cver.

You can download gpl cver from site www.pragmatic-c.com/gpl-cver.
/Steve

<snip>

--
Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email: [email protected]
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402
Reply With Quote
  #5 (permalink)  
Old 11-28-2003, 07:42 AM
Narendran Kumaraguru Nathan
Guest
 
Posts: n/a
Default Re: editing a vcd file

Andy Botterill <[email protected]> wrote in message news:<[email protected]>...
> In article <[email protected] >, Narendran
> Kumaraguru Nathan <[email protected]> writes
> >Hi All,
> > I use the vcd of my simulation to generate test vectors. Now, I have
> >a need to edit a vcd file, to change the values of signals at
> >particular point. I am presently doing that by hand. Does anyone know
> >about any existing tool to do that?

>
> What is the period of the clock signal?


The tool should not depend on the period of the clock signal.

>
> > My actual problem is something like this - assume that reset is
> >asserted to '0' from time 0 to time 30 ns. Signal "A" was '1' from
> >time 0 to time 50 ns. Now, I wish to change the value of signal "A" to
> >'X' during the time when the reset was asserted.... ie. I wish to edit
> >the vcd file such that signal "A" was 'X' from time 0 to time 30 ns
> >and value '1' from time 30 ns to 50 ns...

>
> If the number is reasonably small and the timing is simple then ask the
> test engineer , *very nicely* , and he may do it for you.


The problem becomes complicated when 2 or more signals and different
conditions are evaluated before patching up the original vcd dump.
Also I wish the thing to be automated.

>
> > I don't think a simple script will do the job but still I have heard
> >of some scripts available in perl. Can anybody point me to such
> >scripts / programs?
> > I will also like to know wether anyone else also face similar
> >problems.

>
> Devices are often in a strange state until the first instruction has
> been decoded. I've seen this before.


At least happy to find that I am not the only one who may be facing
such a problem and that gives me hope that someone might have a
solution.

>
> >Thanks & Regards,
> >Naren.


~naren.
Reply With Quote
  #6 (permalink)  
Old 12-01-2003, 06:12 PM
Anthony J Bybell
Guest
 
Posts: n/a
Default Re: editing a vcd file

Steve Meyer <[email protected]> wrote in message news:<[email protected] >...

> gpl cver has a program called vcddiff for 'diffing' two vcd files
> that may help in editing your file. It is released under the
> GNU free software GPL license so you could also use the VCD file reading code
> but it is not separated out as a VCD reading library. If anyone has
> ideas for tools or features needed for maniuplating VCD files (that are not
> patented), we would add it to the vcddiff part of Cver.
>
> You can download gpl cver from site www.pragmatic-c.com/gpl-cver.
> /Steve


Note that where things can get a little bit tricky with VCD files is
that some simulators will occasionally bitblast nets so you'll have to
rechain them back together if you wish to process them like a user
would expect. So if you have a[3:0] in your Verilog, you might get
a[3], a[2], a[1], a[0] in the VCD file. This is one of those things
which could prove problematic when attempting to edit/manipulate VCD
files; it all depends on which simulator is being used.

-t
Reply With Quote
  #7 (permalink)  
Old 12-18-2003, 06:29 PM
Narendran Kumaraguru Nathan
Guest
 
Posts: n/a
Default Re: editing a vcd file

Hi Andy,
Did you come up with a new libvcdparse lib? Or can you elaborate on
this?
How should I do this? Can you direct me to some work/papers which will
be useful for me in doing this?
Thanks,
~naren.


[email protected] (Anthony J Bybell) wrote in message news:<[email protected] om>...
> Andy Botterill <[email protected]> wrote in message news:<[email protected]>...
> > In article <[email protected] >, Narendran
> > Kumaraguru Nathan <[email protected]> writes
> > >Hi All,
> > > I use the vcd of my simulation to generate test vectors. Now, I have
> > >a need to edit a vcd file, to change the values of signals at
> > >particular point. I am presently doing that by hand. Does anyone know
> > >about any existing tool to do that?

>
> I can't think of any offhand though surely somebody out there has
> written such a thing already.
>
> What I do need to do sometime is come up with a libvcdparse library
> such that VCD processing tools will be easy to write. The integrated
> approach in gtkwave--while it works--requires siamese twin separation
> surgery when wishing to develop other tools from the vcd.c code. Hmm,
> I might work on that this weekend as it would greatly simplify the
> implementations of the vcd2whatever converters I have laying around.
>
>
> > > I don't think a simple script will do the job but still I have heard
> > >of some scripts available in perl. Can anybody point me to such
> > >scripts / programs?
> > > I will also like to know wether anyone else also face similar
> > >problems.

> >
> > Devices are often in a strange state until the first instruction has
> > been decoded. I've seen this before.

>
> It sounds like you're misunderstanding him...he wants to generate
> input stimulus from user-modified VCD files. I've done this before at
> work in order to speed up re-simulation of logic fixes. Why sim a
> whole processor if you're working on a fix for a bad corner case in
> branch predict?
>
> 1) run a sim job and generate waves
> 2) step through the wave file and generate a set of test vectors which
> continuously stim all the input ports of your buggy module
> 3) re-compile the module in question and build a model of just it.
> 4) stim the module with the values from #2
> 5) logic fix/repeat at #4 until working
>
> ...I forget who, but somebody actually has a patent on this. It
> obviously doesn't work on all cases, but can be useful as a quick and
> dirty rapid debug solution for logic bugs like missing AND qualifiers
> and the like in control logic or whatever. (Note that I usually do
> sim the fixed logic on the real model afterwards "just in case".)
>
> -t

Reply With Quote
  #8 (permalink)  
Old 12-18-2003, 08:12 PM
Andy Botterill
Guest
 
Posts: n/a
Default Re: editing a vcd file

In article <[email protected] >, Narendran
Kumaraguru Nathan <[email protected]> writes
>Hi Andy,
> Did you come up with a new libvcdparse lib? Or can you elaborate on
>this?


Err I would have done this manually. If the signal names and vcd
identifiers are reasonably constant then a perl script will do quite
nicely.

>How should I do this? Can you direct me to some work/papers which will
>be useful for me in doing this?


I have no papers because I used to do this as part of my job supporting
the company design flows. In general I only had to review the VCD file
data and confirm that the design flow was working correctly and the
pattern extraction process was correct. If not I would say where the
errors were occurring and get the design flow changed.

What are you trying to do? Are you trying to remove X and Z states from
the VCD file so that they do not occur in the extract test pattern file?
Are you trying to move transitions so that they can be created by a
tester? If the second answer is true then it would be better to record
where the problems occur and modify the testbench rather than changing
the VCD file.

Look at the VCD file and see what sort it is? There are two types of VCD
files created by $dumpvars and $dumpports. Chapter 13 of the ModelSim
User's Manual gives a reasonably good explanation of the various types.

VCD files created by $dumpvars do not have any direction information so
you will have to supply that information.

VCD files can contain state information for design modules throughout
multiple levels of a design. Try to keep the number of signals to one
level preferably the topmost level.

Look for the $scope definition. This will allow design signal names to
be related to VCD identifiers.

The format of the VCD file is pretty simple. There is signal
definitions, time and state.

At time 0 (#0) all signals need to be defined. If you are lucky all you
may have to do is to decide what state you need and define that state at
time 0. So once you have moved the definition to time 0 you may delete
the VCD lines. If the purpose of this activity is to move edges and
states around prior to pattern extraction then check that the modified
VCD files edges all change state at the same place relative to the clock
(and tester period).

For $dumpvars created VCD file the states are 0, 1, Z and X. In general
all signals should be driven unless they are in an output state. If you
have bi-directionals you will need to figure out the direction of the
signal.

For $dumpports created VCD files the states are more complicated. The
following states are unknown direction and should be fixed before trying
to do anything to the VCD file.

? unknown (both input and output are driving unknown)
A unknown (input driving low and output driving high)
a unknown (input driving low and output driving unknown)
C unknown (input driving unknown and output driving low)
b unknown (input driving high and output driving unknown)
B unknown (input driving high and output driving low)
c unknown (input driving unknown and output driving high)

f tri-state
Z tri-state
T tri-state
The above states are all tristates and should be converted into a
suitable driven state. If you intend to measure Idd then you could maybe
substitute the pulled state.

N unknown
X unknown
These should be changed to a suitable state.

The other states are defined input and output levels so they shouldn't
be changed.

For input signals make sure that the edges all change at the same time
or you will have problems in the pattern process.

Maybe you could send me a *small* sample of what you are trying to
change and I'll comment further.

ModelSim can be used to re-simulate the files in some conditions. It is
advisable to do this if the changes are extensive.

By the way it may be easier to change the test vectors directly rather
than modifying the VCD file. For a few changes this may be easy to do.
Extensive changes will not be welcomed by the test engineer. Ask very
nicely and see what they say.

>Thanks,
>~naren.


Happy to help.

[snip]
--
Andy Botterill
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On



All times are GMT +1. The time now is 03:17 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved