FPGA Central

Dear Friends,

I am wondered is it possible to generate such a clock with 50% duty
cycle???


Thanks & Regards,
krs...

Yes it is possible; think negedge activated flops.

- Swapnajit.

Hi Swapnajit,

But Divide by 3/2 means, this clock will have "3/4 T" AS its active high
and low edges where "T" is the duraion of the previous clock's period.

I still didn't get any idea.Will you elaborate your idea?

Thanks & Regards,
krs

oops...I should have asked the question more precisely like :

The logic (for divide by 3 clock generation ) should be synthesizable.

Is it possible?

Thanks & Regards,
krs...

rsk wrote:
> oops...I should have asked the question more precisely like :
>
> The logic (for divide by 3 clock generation ) should be synthesizable.
>
> Is it possible?
>
> Thanks & Regards,
> krs...

Try below code:
Cheers,
Pranav

module freq_div (clkin, rst, clkout);
input clkin;
input rst;
output clkout;
wire clkin;
wire rst;
wire clkout;
reg [1:0] cntr;

always @ (negedge clkin)
begin
if (!rst || (cntr==2))
cntr = 0;
else
cntr = cntr + 1;
end

assign clkout = ((!clkin && cntr==0) || (clkin && cntr==0) || (!clkin
&& cntr==1))
? 1'b1 : 0;

endmodule

Hi pranav,

In your code once the "cntr" reaches to "2", it will be latched to "0".

Thanks & Regards
krs...

rsk wrote:
> Hi pranav,
>
> In your code once the "cntr" reaches to "2", it will be latched to "0".
>
> Thanks & Regards
> krs...

Actually it's not "latched" but clocked to zero by the negative
edge of the input clock.

In any case this code divides the clock by 3, not 3/2 (1.5)
which is I believe what you originally asked. You cannot make
an output clock with 50% duty cycle unless you have access to
a quarter-cycle shifted input clock in this case. This would
be possible for example using the DLL in a Xilinx Virtex FPGA,
but without some sort of delay element you're out of luck.

Odd integer clock division with 50% can be done as mentioned
using both edges of the input clock (but to be truly 50% the
input clock must also have 50% duty cycle).

The best you can do without a delay element for divide by 1.5
would be 66.67% duty cycle. Also for the x.5 division cases,
changing the input clock duty cycle from 50% will cause cycle
to cycle jitter in addition to changes in output duty cycle.
This is because the output clock period contains alternately
two input high times plus one input low time, then two input
low times plus one input high time.

In an FPGA, where the D-flip-flop typically has an associated
programmable clock inverter, the easiest way to divide by 1.5
is to use two flip-flops, one on each clock edge like:

always @ (posedge clk) flop1 <= !(flop1 | flop2);

always @ (negedge clk) flop2 <= !(flop1 | flop2);

assign clkout = !(flop1 | flop2);

Although the D function for each flip-flop is the same, you will
see if you simulate this that because they change on alternate
edges of the input clock the Q functions are different, in fact
forming a divide by three clock with 2 non-overlapping phases.