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Old 07-02-2003, 05:29 PM
Anand P Paralkar
Posts: n/a
Default Discrepancy in CLB Usage Report


I am using the following flow:

VHDL - Entry
Synplify Pro - Synthesis
Xilinx Design Manager - Post synthesis, place and route, etc.

The target device is Xilinx Spartan XL - XCS20XL.

I am trying to understand the two summaries:

1. Synthesis Summary
Logic Mapping Summary:
FMAPs: 243 of 392 (62%)
HMAPs: 83 of 196 (43%)
Total packed CLBs: 173 of 196 (89%) <-*-*-*-
(Packed CLBs is determined by the larger of three quantities:
Registers / 2, HMAPs, or FMAPs / 2.)

2. Xilinx Design Manager Summary
Design Summary:
Number of errors: 1
Number of warnings: 6
Number of CLBs: 250 out of 196 127% <-*-*-*-
CLB Flip Flops: 346
CLB Latches: 3
4 input LUTs: 246
3 input LUTs: 230 (147 used as route-throughs)
Number of bonded IOBs: 48 out of 112 42%
IOB Flops: 34
IOB Latches: 0
Number of clock IOB pads: 4 out of 8 50%
Number of TBUFs: 2 out of 448 1%
Number of BUFGLSs: 4 out of 8 50%
32 unrelated functions packed into 31 CLBs.
(12% of the CLBs used are affected.)
Total equivalent gate count for design: 4178
Additional JTAG gate count for IOBs: 2304

Why is there a discrepancy between the Number of CLBs reported
by the synthesis tool (173) and the Xilinx design manager (250)?

As you would observe, the design manager reports an error due
to the excess usage of CLBs. As a result the flow does not proceed
to Place and Route etc. Any suggestions?

Thank you for your time.


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