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Old 10-21-2004, 02:45 PM
Mohammad Ashraf
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Default Diffent timescale resolutions in multiple HDL files

Hello folks,

The way I understood verilog timescale directive works in multiple files is that
it will pickup the smallest in any given HDL file and will use it in the
simulator.

Currently I have a project in which module 1 must have 1ps and module 2 must
have 1fs resolutions. With the curent implementation it uses 1fs resolution
which fails module 1 requirement. (The way module 1 or module 2 are written,
bad practice though).

Is there a way to get around with that. I was hoping at the end of each
module to use something `resettimescale but question is that Simulator can't
deal with multiple resolutions in a given run.

Has someone ever experienced before. Would appreciate sharing your thoughts.

Regards,

Ash
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Old 10-22-2004, 07:20 AM
Vikram
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Default Re: Diffent timescale resolutions in multiple HDL files

[email protected] (Mohammad Ashraf) wrote in message news:<[email protected] com>...
> Hello folks,
>
> The way I understood verilog timescale directive works in multiple files is that
> it will pickup the smallest in any given HDL file and will use it in the
> simulator.
>
> Currently I have a project in which module 1 must have 1ps and module 2 must
> have 1fs resolutions. With the curent implementation it uses 1fs resolution
> which fails module 1 requirement. (The way module 1 or module 2 are written,
> bad practice though).
>
> Is there a way to get around with that. I was hoping at the end of each
> module to use something `resettimescale but question is that Simulator can't
> deal with multiple resolutions in a given run.
>
> Has someone ever experienced before. Would appreciate sharing your thoughts.
>
> Regards,
>
> Ash



Never needed to do this before, but a google search got me this -

" There is no default timescale in Verilog. A module with a missing
timescale is at risk of inheriting an invalid timescale from a
previously compiled module.

Where the LRM talks about delays, add a recommendation to add a
`timescale in front of every module, similarly add a `resetall at the
end of every module to insure that timescales are not inherited by
subsequent modules. This will help identify modules with missing
timescales that might cause simulation timing problems. "

As I uderstand from the above, `resetall will reset all the compiler
directives at the end of the module, including `timescale. I think
most most compilers should support `resetall directive.

HTH,
Vikram.
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