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  #1 (permalink)  
Old 09-01-2006, 05:38 PM
rik
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Default design issue

can you assign a register both from a sequential as well as a
combinational always block?
I mean something like,

always @(reset, posedge tclk)
.........
shiftreg_dr[31:0] <= {tdi_in, shiftreg_dr[31:1];
..........


always @(*)
..........
if (count_shiftin == 31)
shiftreg_dr[31:0] = error_value[31:0];
..........

end

as far as race consition is concerned I dont think it will not affect
this since this events taking place at different conditions.



Rik

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  #2 (permalink)  
Old 09-01-2006, 06:13 PM
Jerry Johns
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Default Re: design issue

hey rik,
from my knowledge, no you cannot do that since thats an
illigal assignment; at the tkcl posedge, shiftreg_dr has two possible
combos, and thats just not right

but what you can do is leave the always assignment in,
and then for your combinational part,

shiftreg_dr_output[31:0] = (count_shiftin==31) ? error_value[31:0] :
shiftreg_dr[31:0];

this will create a mux and a comparator, which will give you ur desired
results;

rik wrote:
> can you assign a register both from a sequential as well as a
> combinational always block?
> I mean something like,
>
> always @(reset, posedge tclk)
> ........
> shiftreg_dr[31:0] <= {tdi_in, shiftreg_dr[31:1];
> .........
>
>
> always @(*)
> .........
> if (count_shiftin == 31)
> shiftreg_dr[31:0] = error_value[31:0];
> .........
>
> end
>
> as far as race consition is concerned I dont think it will not affect
> this since this events taking place at different conditions.
>
>
>
> Rik


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  #3 (permalink)  
Old 09-01-2006, 06:13 PM
Jerry Johns
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Posts: n/a
Default Re: design issue

hey rik,
from my knowledge, no you cannot do that since thats an
illigal assignment; at the tkcl posedge, shiftreg_dr has two possible
combos, and thats just not right

but what you can do is leave the always assignment in,
and then for your combinational part,

shiftreg_dr_output[31:0] = (count_shiftin==31) ? error_value[31:0] :
shiftreg_dr[31:0];

this will create a mux and a comparator, which will give you ur desired
results;

rik wrote:
> can you assign a register both from a sequential as well as a
> combinational always block?
> I mean something like,
>
> always @(reset, posedge tclk)
> ........
> shiftreg_dr[31:0] <= {tdi_in, shiftreg_dr[31:1];
> .........
>
>
> always @(*)
> .........
> if (count_shiftin == 31)
> shiftreg_dr[31:0] = error_value[31:0];
> .........
>
> end
>
> as far as race consition is concerned I dont think it will not affect
> this since this events taking place at different conditions.
>
>
>
> Rik


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  #4 (permalink)  
Old 09-01-2006, 08:20 PM
Guest
 
Posts: n/a
Default Re: design issue


rik wrote:
> can you assign a register both from a sequential as well as a
> combinational always block?


It is legal in the language, but a synthesis tool will presumably
reject it as nonsynthesizable.

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  #5 (permalink)  
Old 09-03-2006, 02:13 AM
rik
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Posts: n/a
Default Re: design issue

Thanks guys, but what about assigning a register in several
combinational always block?
like

always @(.....
begin
shift_reg = buffer_reg;
.......
.......
end

always @(....
begin
shift_reg = dummy_reg
.......
.......
end

Is it synthesizable? I need to assign them at different levels.
rik


[email protected] wrote:
> rik wrote:
> > can you assign a register both from a sequential as well as a
> > combinational always block?

>
> It is legal in the language, but a synthesis tool will presumably
> reject it as nonsynthesizable.


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  #6 (permalink)  
Old 09-03-2006, 02:28 PM
ABC
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Posts: n/a
Default Re: design issue

Hi Rik,
Definitely it is synthesizable. Why you insist of contention type
design scenario?

Best regards,
ABC

rik wrote:
> Thanks guys, but what about assigning a register in several
> combinational always block?
> like
>
> always @(.....
> begin
> shift_reg = buffer_reg;
> .......
> .......
> end
>
> always @(....
> begin
> shift_reg = dummy_reg
> .......
> .......
> end
>
> Is it synthesizable? I need to assign them at different levels.
> rik
>
>
> [email protected] wrote:
> > rik wrote:
> > > can you assign a register both from a sequential as well as a
> > > combinational always block?

> >
> > It is legal in the language, but a synthesis tool will presumably
> > reject it as nonsynthesizable.


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  #7 (permalink)  
Old 09-05-2006, 05:52 AM
johnp
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Posts: n/a
Default Re: design issue

Color me skeptical.

If you think this is synthesizable, you'd better hope that either
a) your manager/peers don't review your code
or
b)

Well, I can;t think of a point (b).

If all the variables in the sensitivity lists change at the same time,
which block wins? You don't know. So you better not try to
synthesize it!

John Providenza


ABC wrote:
> Hi Rik,
> Definitely it is synthesizable. Why you insist of contention type
> design scenario?
>
> Best regards,
> ABC
>
> rik wrote:
> > Thanks guys, but what about assigning a register in several
> > combinational always block?
> > like
> >
> > always @(.....
> > begin
> > shift_reg = buffer_reg;
> > .......
> > .......
> > end
> >
> > always @(....
> > begin
> > shift_reg = dummy_reg
> > .......
> > .......
> > end
> >
> > Is it synthesizable? I need to assign them at different levels.
> > rik
> >
> >
> > [email protected] wrote:
> > > rik wrote:
> > > > can you assign a register both from a sequential as well as a
> > > > combinational always block?
> > >
> > > It is legal in the language, but a synthesis tool will presumably
> > > reject it as nonsynthesizable.


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  #8 (permalink)  
Old 09-05-2006, 02:59 PM
ABC
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Posts: n/a
Default Re: design issue

Hi John,
I believe you are none DC user, might be FPGA user.DC can synthesize it
with error flag to warn user.
Again, you are right regarding option a which is why I ask Rik insist
on using contention type design.

Best regards,
ABC


johnp wrote:
> Color me skeptical.
>
> If you think this is synthesizable, you'd better hope that either
> a) your manager/peers don't review your code
> or
> b)
>
> Well, I can;t think of a point (b).
>
> If all the variables in the sensitivity lists change at the same time,
> which block wins? You don't know. So you better not try to
> synthesize it!
>
> John Providenza
>
>
> ABC wrote:
> > Hi Rik,
> > Definitely it is synthesizable. Why you insist of contention type
> > design scenario?
> >
> > Best regards,
> > ABC
> >
> > rik wrote:
> > > Thanks guys, but what about assigning a register in several
> > > combinational always block?
> > > like
> > >
> > > always @(.....
> > > begin
> > > shift_reg = buffer_reg;
> > > .......
> > > .......
> > > end
> > >
> > > always @(....
> > > begin
> > > shift_reg = dummy_reg
> > > .......
> > > .......
> > > end
> > >
> > > Is it synthesizable? I need to assign them at different levels.
> > > rik
> > >
> > >
> > > [email protected] wrote:
> > > > rik wrote:
> > > > > can you assign a register both from a sequential as well as a
> > > > > combinational always block?
> > > >
> > > > It is legal in the language, but a synthesis tool will presumably
> > > > reject it as nonsynthesizable.


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  #9 (permalink)  
Old 09-05-2006, 04:08 PM
gorjusborg
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Posts: n/a
Default Re: design issue

Hi ABC,
Your insistence that the code in question is synthesizable because you
can run it through Design Compiler (which will then generate an error)
is incorrect.
One could run the text of a cookbook through the tool and it would
raise an error, though I would hope you wouldn't argue that you could
synthesize a cookbook.

In reality, creating a multi-driver bus (which is what the code would
create, if you could synthesize it) it just not good design practice
for ASIC. I've heard that some FPGA synthesis tools could use this
technique to 'mux' logic, by utilizing on-chip hi-impedance buses
(tri-state), but in general, unless you know what you are doing (and
are trying to do something tricky), writing RTL which assigns values to
the same register from more than one always block is not good design
practice.

Brandon

ABC wrote:
> Hi John,
> I believe you are none DC user, might be FPGA user.DC can synthesize it
> with error flag to warn user.
> Again, you are right regarding option a which is why I ask Rik insist
> on using contention type design.
>
> Best regards,
> ABC
>
>
> johnp wrote:
> > Color me skeptical.
> >
> > If you think this is synthesizable, you'd better hope that either
> > a) your manager/peers don't review your code
> > or
> > b)
> >
> > Well, I can;t think of a point (b).
> >
> > If all the variables in the sensitivity lists change at the same time,
> > which block wins? You don't know. So you better not try to
> > synthesize it!
> >
> > John Providenza
> >
> >
> > ABC wrote:
> > > Hi Rik,
> > > Definitely it is synthesizable. Why you insist of contention type
> > > design scenario?
> > >
> > > Best regards,
> > > ABC
> > >
> > > rik wrote:
> > > > Thanks guys, but what about assigning a register in several
> > > > combinational always block?
> > > > like
> > > >
> > > > always @(.....
> > > > begin
> > > > shift_reg = buffer_reg;
> > > > .......
> > > > .......
> > > > end
> > > >
> > > > always @(....
> > > > begin
> > > > shift_reg = dummy_reg
> > > > .......
> > > > .......
> > > > end
> > > >
> > > > Is it synthesizable? I need to assign them at different levels.
> > > > rik
> > > >
> > > >
> > > > [email protected] wrote:
> > > > > rik wrote:
> > > > > > can you assign a register both from a sequential as well as a
> > > > > > combinational always block?
> > > > >
> > > > > It is legal in the language, but a synthesis tool will presumably
> > > > > reject it as nonsynthesizable.


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  #10 (permalink)  
Old 09-06-2006, 01:52 AM
Guest
 
Posts: n/a
Default Re: design issue


ABC wrote:
>
> Definitely it is synthesizable. Why you insist of contention type
> design scenario?


While some synthesis tool might allow this, and produce two pieces of
combinational logic driving the same net in contention, I would not
describe this as synthesizing it. The behavior of the resulting logic
would not be anything like the behavior of the original Verilog code.
A synthesis tool could allow this and produce any random logic it
wants, but unless the logic matches the original behavior reasonably
well, this is not synthesis.

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  #11 (permalink)  
Old 09-06-2006, 03:34 PM
ABC
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Posts: n/a
Default Re: design issue

Hi Sharp,Brandon,
I never agree it is a good practice but just it can synthesize into gln
with error message flag. I do aware of the risk involve for such design
style which is why I questioning Rik. I also know about the usage of
tristate bus and etc.. Please read my reply carefully before anyone
reply my email or start commenting. It is the third person who put such
comment already and it really...

Again. I did question Rik "why you insist of contention type design
scenario" just in case it skip any of yours eyes intentionally or
unintentionally.

It is the last reply from me for such comment and won't entertain it
again.



Best regards,
ABC

[email protected] wrote:
> ABC wrote:
> >
> > Definitely it is synthesizable. Why you insist of contention type
> > design scenario?

>
> While some synthesis tool might allow this, and produce two pieces of
> combinational logic driving the same net in contention, I would not
> describe this as synthesizing it. The behavior of the resulting logic
> would not be anything like the behavior of the original Verilog code.
> A synthesis tool could allow this and produce any random logic it
> wants, but unless the logic matches the original behavior reasonably
> well, this is not synthesis.


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