FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-09-2005, 07:06 PM
Paul Marciano
Guest
 
Posts: n/a
Default Delay style question.

Hi. As a beginner I'd appreciate a critique of my coding style.

always @(posedge clk)
r <= #1 a | b;

wire #1 w = a | b;

assign #1 x = a | b;

always @*
begin
j = #1 a | b;
k = #1 a | b;
end


The delays are, of course, for waveform viewing behavioral simulations.

Looking at other people's code, I see non-blocking delays, but I've not
seen wire, assign and blocking delays (I think the always @* block ends
up with k assigned after #2).

I've also noted some people preferring a `define non-blocking delay
that they can remove to speed up simulation.


So, from a style perspective, what delays do you add in your code and
why? Do you add wire and continuous assign delays or do you just delay
non-blocking assignments? Do you `define your delays?


Thanks for the input.

Paul.

Reply With Quote
  #2 (permalink)  
Old 11-10-2005, 11:25 PM
Guest
 
Posts: n/a
Default Re: Delay style question.

Hi, Paul -

You may want to browse a number of papers on my web page for coding
guidelines and important coding details.

www.sunburst-design.com/papers

Look for the Boston SNUG 2002 paper:
Verilog Nonblocking Assignments With Delays, Myths & Mysteries

Also look for the HDLCon 1999 paper:
Correct Methods For Adding Delays To Verilog Behavioral Models

And one more. Look for the San Jose SNUG 2000 paper:
Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

I do not add delays to any of my RTL or behavioral code. If you follow
all the guidelines in the last paper above, including guideline #5 (see
section 5), and if you apply stimulus from your testbench on the
inactive clock edge (typically negedge clk), then all transitions on
the active clock edge in a waveform display are the result of
registered logic that has changed that may also change downstream
combinational logic. If you violate guideline #5, you will have inputs,
outputs and clocks all changing on the same clock edge, which can be
quite confusing.

Any changes on the negedge clk will be stimulus inputs or combinational
logic that is sensitive to input changes.

Putting delays on the left- or right-hand-side of blocking and most
nonblocking assignments inside of an always block is a very poor coding
style (as detailed in the middle paper above).

If you are trying to model inertial delays, adding delays to continuous
assignments will work.

I have not seen anybody add delays to wire declarations in years.

Regards - Cliff Cummings
Verilog & SystemVerilog Guru
www.sunburst-design.com

Reply With Quote
  #3 (permalink)  
Old 11-11-2005, 06:25 AM
Paul Marciano
Guest
 
Posts: n/a
Default Re: Delay style question.


[email protected] wrote:
> Hi, Paul -
>
> You may want to browse a number of papers on my web page for coding
> guidelines and important coding details.
>
> www.sunburst-design.com/papers


Thanks Cliff. Lots of advice. I'll read those papers.

> I have not seen anybody add delays to wire declarations in years.


As a beginner I reserve the right to make all the usual mistakes :-)

Regards,
Paul.

Reply With Quote
  #4 (permalink)  
Old 11-11-2005, 06:08 PM
Paul Marciano
Guest
 
Posts: n/a
Default Re: Delay style question.


[email protected] wrote:
> Hi, Paul -
>
> You may want to browse a number of papers on my web page for coding
> guidelines and important coding details.
>
> www.sunburst-design.com/papers


Cliff,

I took a look at your site - I had been there before (maybe a year ago)
and I do already follow all of your guildelines.

I use delays in my RTL purely for waveform viewing (my head is screwed
on straight).

Thanks again to pointing me back to your site.

Regards,
Paul.

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Style question - leftshift or not? Paul Marciano Verilog 5 09-27-2005 10:36 PM
which one style is better ? Essen Verilog 1 11-19-2004 04:55 AM
verilog inline delay style question Lawrence Nospam Verilog 1 06-10-2004 06:42 AM
Verilog 2001 coding style question Marco Lazar Verilog 1 01-22-2004 10:49 PM
Transport Delay and Inertial Delay kumar Verilog 0 07-16-2003 03:34 PM


All times are GMT +1. The time now is 06:08 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved