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Old 03-26-2006, 01:44 AM
kb33
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Default defining a range in Verilog

Hi,

I want to do something like

`define RANGE1 >1 && < 4

(meaning that if a value is greater than 1 and less than 4, it would
belong to RANGE1. )
What would be the proper way to write such a construct using the
`define or parameter keywords?

kb33

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Old 03-26-2006, 04:36 AM
mk
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Default Re: defining a range in Verilog

On 25 Mar 2006 16:44:53 -0800, "kb33" <[email protected]>
wrote:

>Hi,
>
>I want to do something like
>
>`define RANGE1 >1 && < 4
>
>(meaning that if a value is greater than 1 and less than 4, it would
>belong to RANGE1. )


Unfortunately this is not possible as the logic necessary to say what
you want reads as:

x > 1 && x < 4

where x is the variable you want to check against the range. What you
can do is to define a rangelow and rangehigh and use them in your code
to read:

`define rangelow 1
`define rangehigh 4

x > `rangelow && x < `rangehigh

Another solution is to use a function

function isinRange1;
input [...] x;

return x > `rangelow && x < `rangehigh;
endfunction

Then you can say

if (isinRange1(x))

etc.

Hth.

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  #3 (permalink)  
Old 03-26-2006, 10:08 PM
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Default Re: defining a range in Verilog

Or a macro with an argument:

`define INRANGE1(x) ((x) > 1 && (x) < 4)

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