FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-10-2008, 12:35 PM
Guest
 
Posts: n/a
Default Decoupled Address and Data Bus

Hi,
"Decoupled address and data buses support split-bus transaction
capability for improved bandwidth"
This is the Statement in one of the Specs Given, I want to Know
1. What is Decoupled Address??
2. Wat is Split Bus Transaction??

How they Improve Bandwidth???

Regards,
RP Yadav
Reply With Quote
  #2 (permalink)  
Old 03-10-2008, 01:42 PM
gabor
Guest
 
Posts: n/a
Default Re: Decoupled Address and Data Bus

On Mar 10, 6:35 am, "[email protected]" <[email protected]>
wrote:
> Hi,
> "Decoupled address and data buses support split-bus transaction
> capability for improved bandwidth"
> This is the Statement in one of the Specs Given, I want to Know
> 1. What is Decoupled Address??


I think they mean the address bus is "decoupled" from the data bus.

In other words the address on the address bus on a particular cycle
does not necessarily correspond to the data on the data bus on
that cycle.

> 2. Wat is Split Bus Transaction??
>


This usually refers to a bus transaction that starts with a
request of some sort (for example "read address 1234") and
then terminates with a completions of some sort (for example
"the data at location 1234 is 5467"). In-between the
request and completion, the transaction doe not make use of
the bus.

> How they Improve Bandwidth???
>


Generally by allowing multiple access to the bus without
waiting for transaction completion. For example if there
were three bus masters trying to read 3 different bus locations
at the same time, and the memory was very slow, each bus
master would briefly use the bus to make its request,
followed by the memory (eventually) returning each of
the requested pieces of data. Without split transaction,
each bus master would need to wait for the memory to
complete the read cycle requested by the previous master,
possibly while the bus sat in some "busy" state.

> Regards,
> RP Yadav


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
auto address increment counter Kunal Verilog 0 06-20-2007 09:18 PM
Data Memory Implementation Mahurshi Akilla Verilog 1 04-19-2007 04:26 AM
read hex data from a file vinoth Verilog 2 03-30-2007 06:24 AM
formatted data leaf Verilog 3 02-07-2006 12:54 AM
PLI: manipulating reg data through VPI Girish Venkataramani Verilog 4 11-17-2003 10:09 PM


All times are GMT +1. The time now is 05:10 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved