FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 05-16-2004, 01:03 PM
Sathyanarayan B
Guest
 
Posts: n/a
Default Converting a vector from one fixed point format to another

Hi,
I am working on RTL implementation of signal processing blocks. It is
generally required to convert a vector in one fixed point format to
another inside such blocks. Also it is generally preferred to have the
signal widths as generics in the initial phases of the design.

Assuming <W,P> format, where P is a constant, there could be 3
conditions:
1. LHS width greater than RHS width
2. LHS width less than RHS width
3. LHS and RHS having same width
(by width I mean W)

Case 3 does not need any additional effort. In the case 1, zeroes must
be added to the LSB bit positions and in the case 2, the number must
be checked for any possible saturations.

The problem I face is that the case (1,2 or 3) is decided at
compilation/ elaboration time since the generics are given as
parameters and hence the wires/signals associated with the other
case/s will be optimised by the synthesis tool. This process also
gives out warning messages, though I know that these warnings will not
affect the functionality of my design.

My real problem is that the number of such warning messages is so high
that I fear that certain other warnings will escape my scrutiny. A
script to extract the other warnings is a good solution but it does
seem to be elegant to me. Please let me know if there is any other
solution to my problem.

Thanks & Regards,
Satya
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On



All times are GMT +1. The time now is 11:25 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2019, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved