FPGA Central

Confluence 0.10.3 includes the initial FNF C model generator.

http://www.confluent.org

The resulting C code is significantly different than that produced by
the pre-FNF generator. For now, there is no VCD, testbench, or piped
simulation interface support.

Some new features:

- New simulator data structure.
- Constructor and destructor functions.
- Init and calculation functions.
- Enables running multiple simulation models at once.
- Provides access to all named signals in a design:
debug = sim.signals.top_level.subsystem1.output2;
- Transition level modeling.
- Calculates values for each transition, not just per clock cycle.
- Built-in FNF primitive functions.

Confluence 0.10.3 includes the Icarus Verilog FNF generator, providing
a path from Verilog to C (not to mention VHDL, NuSMV, and JHDL).

Aside from compilation, the C model generator has not undergone
extensive testing. Bug feedback is appreciated. A code review of the
FNF primitive functions would especially be helpful:

$ fnf -read_fnf out.fnf -write_c out # See out.c for FNF primitives.

Confluence and FNF support for black-boxes, timing constraints,
properties, and SystemC generation are next on the list.

http://www.confluent.org/wiki/doku.php?id=wishlist

-Tom