Clock singals
while synthesizing using XILINX ISE5, using verilog language, i got this
message Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Mcompar__n0003_ALB1:O | NONE(*)(myValid_0_0) | 3 | Mcompar__n0001_ALB:O | NONE(*)(mem_pos_7_0) | 11 | temp:Q | NONE | 22 | clk | BUFGP | 31 | -----------------------------------+------------------------+-------+ (*) These 2 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. I tried to use this constraint as i saw in the refernce, but nothing changed.. i wrote these lines // synthesis attribute clock_signal of myValid_0_0 is no; // synthesis attribute clock_signal of mem_pos_7_0 is no; but when i synthesize it again, nothing changed... Best regards Mandilas Antony |
Re: Clock singals
Mandilas Antony <[email protected]> wrote:
: while synthesizing using XILINX ISE5, using verilog language, i got this : message : Clock Information: : ------------------ : -----------------------------------+------------------------+-------+ : Clock Signal | Clock buffer(FF name) | Load | : -----------------------------------+------------------------+-------+ : Mcompar__n0003_ALB1:O | NONE(*)(myValid_0_0) | 3 | : Mcompar__n0001_ALB:O | NONE(*)(mem_pos_7_0) | 11 | : temp:Q | NONE | 22 | : clk | BUFGP | 31 | : -----------------------------------+------------------------+-------+ : (*) These 2 clock signal(s) are generated by combinatorial logic, : and XST is not able to identify which are the primary clock signals. : Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) : generated by combinatorial logic. : I tried to use this constraint as i saw in the refernce, but nothing : changed.. : i wrote these lines : // synthesis attribute clock_signal of myValid_0_0 is no; : // synthesis attribute clock_signal of mem_pos_7_0 is no; Do you have a net name myValid_0_0 in you design? I guess you have more something like wire [7:0] myValid[3:0]; So give the clock_signal attribute to the right net. Or better use CE and a global clock. Bye -- Uwe Bonnes [email protected] Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- |
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