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Old 07-27-2004, 05:58 PM
Lee
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Default Calculate the count of gate???

Dear all,

After the big help from your guys, my design can be synthesized. Now I
got the gate netlist. Can anybody tell me how to calculate the count
of gates?What tools?

Thanks,
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Old 07-27-2004, 08:01 PM
B. Joshua Rosen
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Default Re: Calculate the count of gate???

On Tue, 27 Jul 2004 08:58:39 -0700, Lee wrote:

> Dear all,
>
> After the big help from your guys, my design can be synthesized. Now I
> got the gate netlist. Can anybody tell me how to calculate the count
> of gates?What tools?
>
> Thanks,


The Xilinx mapper puts a meaningless gate count in the .mrp report file.
I'm sure that Altera does the same thing.

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Old 07-28-2004, 01:34 AM
john jakson
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Default Re: Calculate the count of gate???

"B. Joshua Rosen" <[email protected]> wrote in message news:<[email protected]>. ..
> On Tue, 27 Jul 2004 08:58:39 -0700, Lee wrote:
>
> > Dear all,
> >
> > After the big help from your guys, my design can be synthesized. Now I
> > got the gate netlist. Can anybody tell me how to calculate the count
> > of gates?What tools?
> >
> > Thanks,

>
> The Xilinx mapper puts a meaningless gate count in the .mrp report file.
> I'm sure that Altera does the same thing.


You could go through each line of the useage list and do a dot product
against a known ASIC lib. It does require knowing pretty much what
most lines mean, but for datapath driven logic thats usually the case.

Another much cruder 1st attempt is to just use the FF count and mul by
some fudge factor for the type of design.

In the case of a pipelined design where all FFs have same count as
LUTs then use 2FF.

Rams & multipliers though have to be accounted for separately.

regards

johnjakson_usa_com
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  #4 (permalink)  
Old 07-28-2004, 09:07 AM
glen herrmannsfeldt
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Default Re: Calculate the count of gate???

Lee wrote:

> After the big help from your guys, my design can be synthesized. Now I
> got the gate netlist. Can anybody tell me how to calculate the count
> of gates?What tools?


For non-programmable logic, one measures gate count by
comparing some measure of the system to a similar measure
for a two input NAND gate. For CMOS, NAND2 takes four
transistors so it is transistors divided by four.

It is harder to make a fair measuring system for
programmable logic.

-- glen

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