FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-17-2004, 07:55 PM
Carl W.
Guest
 
Posts: n/a
Default Cadence recordvars with Synopsys VCS?


I've been unsuccessful in getting Cadence's recordvars PLI
to work with Synopsys VCS, possibly because I'm doing a very large
gate sim in VCS and recordvars apparently tries to allocate memory
for every node in the sim, not just the ones I want to output. I'm
using the "depth=1" option on the top level module, which isn't
that many nets, but it fails with a message about running out of
memory with 'new'.

What's the best way to create a compressed dumpfile similar
to Cadence's SST2 format in VCS?

Thanks,
Carl
Reply With Quote
  #2 (permalink)  
Old 09-19-2004, 11:48 AM
Petter Gustad
Guest
 
Posts: n/a
Default Re: Cadence recordvars with Synopsys VCS?

"Carl W." <[email protected]> writes:

> I've been unsuccessful in getting Cadence's recordvars PLI
> to work with Synopsys VCS, possibly because I'm doing a very large
> gate sim in VCS and recordvars apparently tries to allocate memory
> for every node in the sim, not just the ones I want to output. I'm
> using the "depth=1" option on the top level module, which isn't
> that many nets, but it fails with a message about running out of
> memory with 'new'.
>
> What's the best way to create a compressed dumpfile similar
> to Cadence's SST2 format in VCS?


I have never noticed that it allocates memory for all nets (have you
got this confirmed from Cadence?), but I guess "very large" is
probably bigger than most of my gate level sims. This is what I
usually do:

$recordsetup("design=testbench","version=1","run=1 ","compress");
$recordvars("depth=1",testbench.top.core.whatever) ;

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Reply With Quote
  #3 (permalink)  
Old 09-21-2004, 06:17 AM
Swapnajit Mittra
Guest
 
Posts: n/a
Default Re: Cadence recordvars with Synopsys VCS?

"Carl W." <[email protected]> wrote in message news:<[email protected]>...
> I've been unsuccessful in getting Cadence's recordvars PLI
> to work with Synopsys VCS, possibly because I'm doing a very large
> gate sim in VCS and recordvars apparently tries to allocate memory
> for every node in the sim, not just the ones I want to output. I'm
> using the "depth=1" option on the top level module, which isn't
> that many nets, but it fails with a message about running out of
> memory with 'new'.
>
> What's the best way to create a compressed dumpfile similar
> to Cadence's SST2 format in VCS?
>
> Thanks,
> Carl


If you are willing to use Virsim, the waveform viewer that
comes free of cost with VCS, you can create a dump in
'vpd' format. Check virsim manual in your VCS installation
documentation.

Virsim is very similar to Signalscan, but personally I find
the later more user friendly.

- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.com
For subscribing to the mailing list:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
how to generate sdf file in cadence buildgates? Carson Verilog 2 05-14-2005 02:46 PM
Question on $random usage in Cadence NC Verilog Doug Hillmer Verilog 2 09-11-2004 01:58 AM
PCB CADENCE ORCAD 2004 - 2000, Altium P-CAD V2002, DXP SUITE V2004, WEBSPHERE EVERYPLACE MOBILE PORTAL v5.0 (c) ALTIUM [2 CDs], ModelSim.SE.v6.0, AutoTRAX.EDA.v3.04, Aldec.Riviera.v2004.08.1533.WinNT2kXP, Metrowerks CodeWarrior Development Studio v Zorba.GR Verilog 0 09-08-2004 07:05 PM
Problem using $recordvars/$recordfile under NCverilog danny_isr Verilog 3 07-01-2004 07:37 PM
Problem with Cadence AMS simulator Guneet Singh Verilog 4 12-22-2003 04:24 AM


All times are GMT +1. The time now is 11:25 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2019, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved