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Old 10-17-2009, 04:45 AM
Daku
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Default C structs in Verilog ?

I was wondering if C-style structs are supported in Verilog. I am
trying to design a packet queue, and
was wondering what the best way to achieve it. I could have a reg of
some size, and assign different values to different subsets of bits.
Any hints suggestions would be greatly apprecaited, and thanks in
advance for your help.
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  #2 (permalink)  
Old 10-17-2009, 12:07 PM
Jonathan Bromley
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Default Re: C structs in Verilog ?

On Fri, 16 Oct 2009 20:45:57 -0700 (PDT), Daku <[email protected]>
wrote:

>I was wondering if C-style structs are supported in Verilog. I am
>trying to design a packet queue, and
>was wondering what the best way to achieve it. I could have a reg of
>some size, and assign different values to different subsets of bits.
>Any hints suggestions would be greatly apprecaited, and thanks in
>advance for your help.


SystemVerilog has structs very similar to the C arrangement
(no struct tags, though; just use typedef in the sensible way).
Many synthesis and simulation tools have built-in support
for this and other synthesizable SystemVerilog constructs,
but you need (a) to check the level of support in your tool,
(b) to ensure that you enable SystemVerilog compilation on
the command line or tool options.

As you say, you can easily enough fake it up in regular Verilog.
A bit of trickery with `define can help a lot.
Suppose I want to describe a control register with this layout:
bits [7:5] : fieldA
bit [4] : fieldB
bits [3:0] : fieldC

Here's a sketch:

`define A_WIDTH 3
`define B_WIDTH 1
`define C_WIDTH 4

reg [`A_WIDTH-1:0] fieldA;
reg [`B_WIDTH-1:0] fieldB;
reg [`C_WIDTH-1:0] fieldC;

// Now start assembling the whole thing right-to-left:

`define C_LSB 0
`define C_MSB (`C_LSB+`C_WIDTH-1)
`define FIELD_C `C_MSB:`C_LSB

`define B_LSB (`C_MSB+1)
`define B_MSB (`B_LSB+`B_WIDTH-1)
`define FIELD_B `B_MSB:`B_LSB

`define A_LSB (`B_MSB+1)
`define A_MSB (`A_LSB+`A_WIDTH-1)
`define FIELD_A `A_MSB:`A_LSB

reg [`A_MSB:`C_LSB] whole;

// OK, now we're ready to go....

// Concatenation to assemble the "struct":
whole = {fieldA, fieldB, fieldC};
// Part select to extract parts of the struct:
fieldA = whole[`FIELD_A];
// Modify just one part of the struct:
whole[`FIELD_B] = 1'b0;
// Unpack the whole struct into separate regs:
{fieldA, fieldB, fieldC} = whole;

In SystemVerilog it's easier:

typedef reg [3:0] fieldA_type;
typedef reg fieldB_type;
typedef reg [2:0] fieldC_type;

typedef struct packed {
fieldC_type C;
fieldB_type B;
fieldA_type A;
} whole_type;

whole_type whole;
fieldA_type fieldA;
fieldB_type fieldB;
fieldC_type fieldC;

...

// Because the struct is packed, I can still treat
// it as if it were a vector:
whole = {fieldA, fieldB, fieldC};
// Part select to extract parts of the struct:
fieldA = whole.A;
// Modify just one part of the struct:
whole.B = 1'b0;
// Unpack the whole struct into separate regs:
{fieldA, fieldB, fieldC} = whole;

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #3 (permalink)  
Old 10-18-2009, 03:37 AM
Daku
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Posts: n/a
Default Re: C structs in Verilog ?


Thanks,
That was very helpful.

On Oct 17, 4:07 pm, Jonathan Bromley <[email protected]>
wrote:
> On Fri, 16 Oct 2009 20:45:57 -0700 (PDT), Daku <[email protected]>
> wrote:
>
> >I was wondering if C-style structs are supported in Verilog. I am
> >trying to design a packet queue, and
> >was wondering what the best way to achieve it. I could have a reg of
> >some size, and assign different values to different subsets of bits.
> >Any hints suggestions would be greatly apprecaited, and thanks in
> >advance for your help.

>
> SystemVerilog has structs very similar to the C arrangement
> (no struct tags, though; just use typedef in the sensible way).
> Many synthesis and simulation tools have built-in support
> for this and other synthesizable SystemVerilog constructs,
> but you need (a) to check the level of support in your tool,
> (b) to ensure that you enable SystemVerilog compilation on
> the command line or tool options.
>
> As you say, you can easily enough fake it up in regular Verilog.
> A bit of trickery with `define can help a lot.
> Suppose I want to describe a control register with this layout:
> bits [7:5] : fieldA
> bit [4] : fieldB
> bits [3:0] : fieldC
>
> Here's a sketch:
>
> `define A_WIDTH 3
> `define B_WIDTH 1
> `define C_WIDTH 4
>
> reg [`A_WIDTH-1:0] fieldA;
> reg [`B_WIDTH-1:0] fieldB;
> reg [`C_WIDTH-1:0] fieldC;
>
> // Now start assembling the whole thing right-to-left:
>
> `define C_LSB 0
> `define C_MSB (`C_LSB+`C_WIDTH-1)
> `define FIELD_C `C_MSB:`C_LSB
>
> `define B_LSB (`C_MSB+1)
> `define B_MSB (`B_LSB+`B_WIDTH-1)
> `define FIELD_B `B_MSB:`B_LSB
>
> `define A_LSB (`B_MSB+1)
> `define A_MSB (`A_LSB+`A_WIDTH-1)
> `define FIELD_A `A_MSB:`A_LSB
>
> reg [`A_MSB:`C_LSB] whole;
>
> // OK, now we're ready to go....
>
> // Concatenation to assemble the "struct":
> whole = {fieldA, fieldB, fieldC};
> // Part select to extract parts of the struct:
> fieldA = whole[`FIELD_A];
> // Modify just one part of the struct:
> whole[`FIELD_B] = 1'b0;
> // Unpack the whole struct into separate regs:
> {fieldA, fieldB, fieldC} = whole;
>
> In SystemVerilog it's easier:
>
> typedef reg [3:0] fieldA_type;
> typedef reg fieldB_type;
> typedef reg [2:0] fieldC_type;
>
> typedef struct packed {
> fieldC_type C;
> fieldB_type B;
> fieldA_type A;
> } whole_type;
>
> whole_type whole;
> fieldA_type fieldA;
> fieldB_type fieldB;
> fieldC_type fieldC;
>
> ...
>
> // Because the struct is packed, I can still treat
> // it as if it were a vector:
> whole = {fieldA, fieldB, fieldC};
> // Part select to extract parts of the struct:
> fieldA = whole.A;
> // Modify just one part of the struct:
> whole.B = 1'b0;
> // Unpack the whole struct into separate regs:
> {fieldA, fieldB, fieldC} = whole;
>
> HTH
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> [email protected]://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


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