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Old 06-09-2004, 06:35 PM
Srinivasan Venkataramanan
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Default Bug in AUTOSENSE with Emacs + Verilog Mode

Hi,
I use the Verilog mode with Emacs from verilog.com, and am quite
happy with it. I found an issue with AUTOSENSE feature, has any one
faced it before? If so are there any fixed release available? Here is
a sample Verilog code to demonstrate the problem. Basically, AUTOSENSE
tends to include "local variables" within in a named always block into
sensitivity list. I have the following controls set (as I need them).

(set-variable (quote verilog-auto-sense-include-inputs) 1)
(set-variable (quote verilog-auto-sense-defines-constant) 0)

Thanks a lot in advance for any fix.
Srinivasan
P.S. if you reply by e-mail, please use srinivasan.venkataramanan AT
intel DOT com - Thanks

module auto();
reg a,b;

always @(/*AUTOSENSE*/b or i) // I didn't expect to get "i" in
AUTOSENSE result
begin : label
integer i, j;

for (i=0; i<= 3; i = i + 1)
vec[i] = b;
end

endmodule
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  #2 (permalink)  
Old 06-10-2004, 02:44 PM
Srinivasan Venkataramanan
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Default Re: Bug in AUTOSENSE with Emacs + Verilog Mode

Sorry to reply to my own posting, through an e-mail (Thanks to Michael) I
learnt that verilog-mode Version 3.61 fixes this issue.

Thanks,
Srini

"Srinivasan Venkataramanan" <[email protected]> wrote in message
news:[email protected] om...
> Hi,
> I use the Verilog mode with Emacs from verilog.com, and am quite
> happy with it. I found an issue with AUTOSENSE feature, has any one
> faced it before? If so are there any fixed release available? Here is
> a sample Verilog code to demonstrate the problem. Basically, AUTOSENSE
> tends to include "local variables" within in a named always block into
> sensitivity list. I have the following controls set (as I need them).
>
> (set-variable (quote verilog-auto-sense-include-inputs) 1)
> (set-variable (quote verilog-auto-sense-defines-constant) 0)
>
> Thanks a lot in advance for any fix.
> Srinivasan
> P.S. if you reply by e-mail, please use srinivasan.venkataramanan AT
> intel DOT com - Thanks
>
> module auto();
> reg a,b;
>
> always @(/*AUTOSENSE*/b or i) // I didn't expect to get "i" in
> AUTOSENSE result
> begin : label
> integer i, j;
>
> for (i=0; i<= 3; i = i + 1)
> vec[i] = b;
> end
>
> endmodule



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