FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > Verilog

Verilog comp.lang.verilog newsgroup / usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-16-2005, 01:57 PM
Sen-Lung Chen
Guest
 
Posts: n/a
Default assign value to register

I have writed a verilog code,the function of the code is to fine the
last one bit of Conf_reg is 1.
for example:
Conf_reg[5:1] = 5'b10101;
the answer Mux_reg = 2'b11;it count from the second bit of Conf_reg,

reg [5:1]Conf_reg;
reg [2:1]Mux_reg;

integer k;
[email protected](Conf_reg)
begin
temp = 2'b00;
for(k=2;k<=5;k=k+1)
if (Conf_reg[k] == 1'b1)
begin
temp = temp+2'b01;
Mux_reg[1] = temp[1];
Mux_reg[2] = temp[2];
end
else
temp = temp+2'b01;
end
endmodule

However,it fails when I compile it.
The error message is as below:
Error! Illegal left-hand-side assignment [Verilog-ILHSA]
"re_LFSR.v", 101: Mux_reg[1] = temp[1];


Error! Illegal left-hand-side assignment [Verilog-ILHSA]
"re_LFSR.v", 102: Mux_reg[2] = temp[2];


How should I fix the program?
Thanks!

Reply With Quote
  #2 (permalink)  
Old 09-16-2005, 04:40 PM
Sen-Lung Chen
Guest
 
Posts: n/a
Default Re: assign value to register

I modified the problem into a simply question.
I want to find the maximun bit of Conf_reg which is 1.
for example :
Conf_reg[4:0] = 5'b10101; [1:0] Mux_reg;
According to the below equation,
Final,k == 3;therefore ,Mux_reg = 2'b11;




[email protected](Conf_reg)
begin
for(k=0;k<=3;k=k+1)
if (Conf_reg[k+1] == 1'b1)
Mux_reg = 2'dk;
end
endmodule


However it fails in compile.
The error message is syntex error in this line 'Mux_reg = 2'dk'
How should I fix the problem?
Thanks

Reply With Quote
  #3 (permalink)  
Old 09-16-2005, 07:28 PM
Art Stamness
Guest
 
Posts: n/a
Default Re: assign value to register

That is because the lexical convention expects a [0-9] value after 2'd.

try this :

reg [3:0] k ;
[email protected](Conf_reg)
begin
for(k=0;k<=3;k=k+1)
if (Conf_reg[k+1] == 1'b1)
Mux_reg = k[1:0];
end

This should have a properly sized reg k, used for your loop, and will
assign exactly the two bits you want.

Another far more common practice is to code this example like :

module count_msz ( bit_sel, val ) ;
output [2:0] bit_sel ;
input [7:0] val ;
reg [2:0] bit_sel ;
always @(val)
ca*** ( val )
8'b1xxxxxxx: bit_sel = 3'd7 ;
8'b01xxxxxx: bit_sel = 3'd6 ;
8'b001xxxxx: bit_sel = 3'd5 ;
8'b0001xxxx: bit_sel = 3'd4 ;
8'b00001xxx: bit_sel = 3'd3 ;
8'b000001xx: bit_sel = 3'd2 ;
8'b0000001x: bit_sel = 3'd1 ;
8'b00000001: bit_sel = 3'd0 ;
8'b00000000:
default : bit_sel = 'bx ;
endcase
endmodule

-Art

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
vpi_put_value does not assign value to a vpiPartSelect Henry Verilog 0 01-22-2005 07:08 AM
xst: assign Jan Bruns Verilog 6 10-11-2004 07:47 PM
assign statement in netlist rajan Verilog 4 09-01-2004 12:13 PM
Trying to monitor output of a register instantiates another register seanadams Verilog 1 02-11-2004 06:13 PM
How to assign an array to a vector? Peng Yu Verilog 2 08-06-2003 07:50 PM


All times are GMT +1. The time now is 12:26 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2019, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved