That is because the lexical convention expects a [0-9] value after 2'd.

try this :

reg [3:0] k ;

[email protected](Conf_reg)

begin

for(k=0;k<=3;k=k+1)

if (Conf_reg[k+1] == 1'b1)

Mux_reg = k[1:0];

end

This should have a properly sized reg k, used for your loop, and will

assign exactly the two bits you want.

Another far more common practice is to code this example like :

module count_msz ( bit_sel, val ) ;

output [2:0] bit_sel ;

input [7:0] val ;

reg [2:0] bit_sel ;

always @(val)

ca*** ( val )

8'b1xxxxxxx: bit_sel = 3'd7 ;

8'b01xxxxxx: bit_sel = 3'd6 ;

8'b001xxxxx: bit_sel = 3'd5 ;

8'b0001xxxx: bit_sel = 3'd4 ;

8'b00001xxx: bit_sel = 3'd3 ;

8'b000001xx: bit_sel = 3'd2 ;

8'b0000001x: bit_sel = 3'd1 ;

8'b00000001: bit_sel = 3'd0 ;

8'b00000000:

default : bit_sel = 'bx ;

endcase

endmodule

-Art