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  #1 (permalink)  
Old 05-17-2004, 02:56 PM
DW
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Default Assert in verilog

As a 'C' programmer, I am fond of using asserts - is there an equivalent in
Verilog so I can for example check for appropriate parameter values in my
modules? I have looked but the results were a little confusing.


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  #2 (permalink)  
Old 05-17-2004, 07:04 PM
Nahum Barnea
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Default Re: Assert in verilog

"DW" <[email protected]> wrote in message news:<[email protected]>...
> As a 'C' programmer, I am fond of using asserts - is there an equivalent in
> Verilog so I can for example check for appropriate parameter values in my
> modules? I have looked but the results were a little confusing.


You can always check a value od signal with 'if' statement and report
with '$display'.

You should however wrap it with preprocessor directive `ifdef cause it
is not synthesizable.
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Old 05-18-2004, 09:59 AM
DW
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Default Re: Assert in verilog

Thanks, I'll give this a try
"Nahum Barnea" <[email protected]> wrote in message
news:[email protected] om...
> "DW" <[email protected]> wrote in message

news:<[email protected]>...
> > As a 'C' programmer, I am fond of using asserts - is there an equivalent

in
> > Verilog so I can for example check for appropriate parameter values in

my
> > modules? I have looked but the results were a little confusing.

>
> You can always check a value od signal with 'if' statement and report
> with '$display'.
>
> You should however wrap it with preprocessor directive `ifdef cause it
> is not synthesizable.



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  #4 (permalink)  
Old 05-19-2004, 03:32 AM
Allan Herriman
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Default Re: Assert in verilog

On Tue, 18 May 2004 09:59:16 +0100, "DW" <[email protected]>
wrote:

>Thanks, I'll give this a try
>"Nahum Barnea" <[email protected]> wrote in message
>news:[email protected] com...
>> "DW" <[email protected]> wrote in message

>news:<[email protected]>.. .
>> > As a 'C' programmer, I am fond of using asserts - is there an equivalent

>in
>> > Verilog so I can for example check for appropriate parameter values in

>my
>> > modules? I have looked but the results were a little confusing.

>>
>> You can always check a value od signal with 'if' statement and report
>> with '$display'.
>>
>> You should however wrap it with preprocessor directive `ifdef cause it
>> is not synthesizable.


I experimented with XST. It merely ignored the $display, so there is
no need to use the preprocessor in that way.
What do other synthesisers do?

Regards,
Allan.
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  #5 (permalink)  
Old 05-20-2004, 08:27 AM
Jonathan Bromley
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Default Re: Assert in verilog

On Wed, 19 May 2004 12:32:27 +1000, Allan Herriman
<[email protected]> wrote:


>I experimented with XST. It merely ignored the $display, so there is
>no need to use the preprocessor in that way.
>What do other synthesisers do?


AFAIK all synth tools simply ignore $... system tasks.
However, you still sometimes need `ifdef because you
often need to wrap your $display in a bit more logic
to do the assertion in the way you want.

SystemVerilog has a full-fledged assertion mechanism. It should
be pretty easy for tool vendors to support (==ignore, in synth)
those constructs, so I guess we'll see it supported quite soon.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #6 (permalink)  
Old 05-20-2004, 09:17 AM
DW
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Default Re: Assert in verilog

"Jonathan Bromley" <[email protected]> wrote in message
news:[email protected]
> On Wed, 19 May 2004 12:32:27 +1000, Allan Herriman
> <[email protected]> wrote:
>
>
> >I experimented with XST. It merely ignored the $display, so there is
> >no need to use the preprocessor in that way.
> >What do other synthesisers do?

>
> AFAIK all synth tools simply ignore $... system tasks.
> However, you still sometimes need `ifdef because you
> often need to wrap your $display in a bit more logic
> to do the assertion in the way you want.
>
> SystemVerilog has a full-fledged assertion mechanism. It should
> be pretty easy for tool vendors to support (==ignore, in synth)
> those constructs, so I guess we'll see it supported quite soon.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
> Tel: +44 (0)1425 471223 mail:[email protected]
> Fax: +44 (0)1425 471573 Web: http://www.doulos.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Yes, I was thinking of an assert which would raise an error when
synthesizing - not when simulating. Basically I want to raise an error if a
particular combination of (potentially defparam overriden) parameter values
is incorrect, so there would be no point continuing with the compilation.
I'm really surprised that this is not built in.

Thankyou.


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  #7 (permalink)  
Old 05-20-2004, 11:47 AM
Jonathan Bromley
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Posts: n/a
Default Re: Assert in verilog

On Thu, 20 May 2004 09:17:56 +0100, "DW"
<[email protected]> wrote:

> I was thinking of an assert which would raise an error when
>synthesizing - not when simulating. Basically I want to
> raise an error if a particular combination of (potentially
> defparam overriden) parameter values is incorrect, so
> there would be no point continuing with the compilation.


Consider using VHDL. I frequently use VHDL assertions for
exactly this purpose. It's a great approach, and synthesis
tools give you appropriate messages.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #8 (permalink)  
Old 05-20-2004, 03:57 PM
DW
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Posts: n/a
Default Re: Assert in verilog

"Jonathan Bromley" <[email protected]> wrote in message
news:[email protected]
> On Thu, 20 May 2004 09:17:56 +0100, "DW"
> <[email protected]> wrote:
>
> > I was thinking of an assert which would raise an error when
> >synthesizing - not when simulating. Basically I want to
> > raise an error if a particular combination of (potentially
> > defparam overriden) parameter values is incorrect, so
> > there would be no point continuing with the compilation.

>
> Consider using VHDL. I frequently use VHDL assertions for
> exactly this purpose. It's a great approach, and synthesis
> tools give you appropriate messages.
> --
> Jonathan Bromley, Consultant
>

We have made a decision to use Verilog for all new designs, so using VHDL is
out of the question. Whether this is a good decision remains to be seen,
but so far I'm quite impressed with Verilog (setting apart this particular
limitation).


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