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Old 11-29-2006, 07:46 PM
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Default array of instances


Does anyone know how array of instance works in verilog?

For example:

I found an example like this:

wire[2:0] in;
wire[2:0] out;
wire ctrl;

bufif0 u[2:0] (out, in, ctrl);

I read that Each primitive instantiation is done separately, and
actually this equals to:

bufif0 u2 (out[2], in[2], ctrl);
bufif0 u1 (out[1], in[1], ctrl);
bufif0 u0 (out[0], in[0], ctrl);

How does verilog "know" to divide out to 3 for 3 instances, but to
connect all instances to ctrl (which is only one bit)?

How does it work?

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