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Old 03-10-2005, 05:13 AM
thomasc
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Default Array input problem

I need to pass an array to a module from a higher level module. But as long
as I know, it is not allowed in Verilog.
Is there any typical way to pass an array as an input to a module(such as
using loop)?

Thank you!


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Old 03-10-2005, 06:35 AM
Paul Uiterlinden
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Default Re: Array input problem

thomasc wrote:
> I need to pass an array to a module from a higher level module. But as long
> as I know, it is not allowed in Verilog.
> Is there any typical way to pass an array as an input to a module(such as
> using loop)?


http://www.google.com/groups?as_q=pa...ilog&lr=&hl=nl
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Old 03-10-2005, 06:16 PM
glen herrmannsfeldt
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Default Re: Array input problem

thomasc wrote:

> I need to pass an array to a module from a higher level module. But as long
> as I know, it is not allowed in Verilog.
> Is there any typical way to pass an array as an input to a module(such as
> using loop)?


What hardware function are you trying to design. That should
give a hint as to how you should pass the array.

Imagine building your system out of 74xx TTL gates, what would
your array look like?

-- glen

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