"John_H" <

[email protected]> wrote in message

news:

[email protected]
[snip]

> If, on the other hand, you don't want to bother with the memory at all you

> could figure out the digits through logic and do the binary to BCD and BCD

> to 7-segment conversions in the chip. The binary-to-BCD is a bit tough

> because it involves division through the three stages to get your digits.
[snip]

I integrated the conversion into a divider-like structure. Getting the BCD

bits out directly is a few stages of add/subtract cascaded together.

Apologies to those who don't like to see lots of code. The file looks best

in fixed space font.

The "top" module is a quick testbench to show that everything works. The

resources and delays are a little excessive for the 8-bit binary to bcd

conversion but the result can be combinatorial. No clock required.

If there are questions about the code, feel free to ask but please don't

repost the whole code to be kind to others.

Thanks,

- John_H

module SevenSeg ( bin

, Seg7_2, Seg7_1, Seg7_0

);

input [7:0] bin;

output [6:0] Seg7_2;

output [6:0] Seg7_1;

output [6:0] Seg7_0;

wire [8:0] res200;

wire [7:0] res100;

wire [6:0] res80;

wire [5:0] res40;

wire [4:0] res20;

wire [3:0] res10;

wire [1:0] bcd2;

wire [3:0] bcd1;

wire [3:0] bcd0;

assign {bcd2[1],res200} = 9'd199 - bin; // 1 offset makes sign work

assign {bcd2[0],res100} = res200 + (bcd2[1] ? 9'd100 : 9'd100-9'd200);

assign {bcd1[3],res80 } = res100 + (bcd2[0] ? 8'd80 : 8'd80 -8'd100);

assign {bcd1[2],res40 } = res80 + (bcd1[3] ? 7'd40 : 7'd40 -7'd80 );

assign {bcd1[1],res20 } = res40 + (bcd1[2] ? 6'd20 : 6'd20 -6'd40 );

assign {bcd1[0],res10 } = res20 + (bcd1[1] ? 5'd10 : 5'd10 -5'd20 );

assign bcd0 = (bcd1[0] ? -4'd1 : 4'd9) - res10;

assign Seg7_2 = hex_to_7( bcd2 );

assign Seg7_1 = hex_to_7( bcd1 );

assign Seg7_0 = hex_to_7( bcd0 );

function [6:0] hex_to_7;

input [3:0] digit;

case(digit) // common anode: {t,rt,rb,b,lb,lt,m}

4'h0: hex_to_7 = 7'b0000001; // ---t---

4'h1: hex_to_7 = 7'b1001111; // | |

4'h2: hex_to_7 = 7'b0010010; // lt rt

4'h3: hex_to_7 = 7'b0000110; // | |

4'h4: hex_to_7 = 7'b1001100; // ---m---

4'h5: hex_to_7 = 7'b0100100; // | |

4'h6: hex_to_7 = 7'b0100000; // lb rb

4'h7: hex_to_7 = 7'b0001111; // | |

4'h8: hex_to_7 = 7'b0000000; // ---b---

4'h9: hex_to_7 = 7'b0001100;

4'hA: hex_to_7 = 7'b0001000;

4'hb: hex_to_7 = 7'b1100000;

4'hC: hex_to_7 = 7'b0110001;

4'hd: hex_to_7 = 7'b1000010;

4'hE: hex_to_7 = 7'b0110000;

4'hF: hex_to_7 = 7'b0111000;

endcase

endfunction

endmodule

module top();

integer i;

wire [6:0] Seg7_2, Seg7_1, Seg7_0;

initial

for( i=0; i<256; i=i+1 )

begin

#1 $display( " %c %c %c", Seg7_2[6] ? " " : "_"

, Seg7_1[6] ? " " : "_"

, Seg7_0[6] ? " " : "_"

);

$display( "%3d %c%c%c%c%c%c%c%c%c", i

, Seg7_2[1]? " ":"|", Seg7_2[0]? " ":"_", Seg7_2[5]? " ":"|"

, Seg7_1[1]? " ":"|", Seg7_1[0]? " ":"_", Seg7_1[5]? " ":"|"

, Seg7_0[1]? " ":"|", Seg7_0[0]? " ":"_", Seg7_0[5]? " ":"|"

);

$display( " %c%c%c%c%c%c%c%c%c"

, Seg7_2[2]? " ":"|", Seg7_2[3]? " ":"_", Seg7_2[4]? " ":"|"

, Seg7_1[2]? " ":"|", Seg7_1[3]? " ":"_", Seg7_1[4]? " ":"|"

, Seg7_0[2]? " ":"|", Seg7_0[3]? " ":"_", Seg7_0[4]? " ":"|"

);

end

SevenSeg Disp ( .bin(i)

, .Seg7_2(Seg7_2)

, .Seg7_1(Seg7_1)

, .Seg7_0(Seg7_0)

);

endmodule