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  #1 (permalink)  
Old 07-21-2009, 01:17 AM
Joel Brown
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Posts: n/a
Default [SI-LIST] Altera PDN Tool

I have been playing around with the Altera PDN tool.
When I look at the ESR and ESL values on the Library page it seems the
values match very closely with AVX SpiCap3 which makes me think that is were
the values came from.

When I used Kemet's spice program I get values that are quite different. One
which stood out was an ESL of 1.9nh for a .01uF 0402 capacitor.

So it makes me wonder if I use the values in the Altera library if the
results are going to be anywhere close to reality especially if we are
buying capacitors from Kemet or another vendor.

I am assuming the ESL values in the Altera library don't include the
mounting inductance since they model that separately.

Is there any information comparing ESL from different capacitor vendors for
0402 or any other size capacitors?



Thanks - Joel









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  #2 (permalink)  
Old 07-21-2009, 01:41 AM
steve weir
Guest
 
Posts: n/a
Default [SI-LIST] Re: Altera PDN Tool

Joel, Altera's PDN team is quite conscientious. While I have not run
the conventional caps through their paces on that tool, the X2Y results
are trustworthy.

An ESL of 1.9nH for an 0402 capacitor would reflect a high mounting
inductance and would not be anything like what you would see in a
shorted plate measurement, which is the basis for most datasheet ESL
values. You'll get 1.9nH or there abouts with a well mounted 0402 if
the vias have to extend about 70mils from the cap mounting surface to
the power cavity.

Best Regards,


Steve.
Joel Brown wrote:
> I have been playing around with the Altera PDN tool.
> When I look at the ESR and ESL values on the Library page it seems the
> values match very closely with AVX SpiCap3 which makes me think that is were
> the values came from.
>
> When I used Kemet's spice program I get values that are quite different.. One
> which stood out was an ESL of 1.9nh for a .01uF 0402 capacitor.
>
> So it makes me wonder if I use the values in the Altera library if the
> results are going to be anywhere close to reality especially if we are
> buying capacitors from Kemet or another vendor.
>
> I am assuming the ESL values in the Altera library don't include the
> mounting inductance since they model that separately.
>
> Is there any information comparing ESL from different capacitor vendors for
> 0402 or any other size capacitors?
>
>
>
> Thanks - Joel
>
>
>
>
>
>
>
>
>
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>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
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  #3 (permalink)  
Old 07-21-2009, 05:15 PM
earl albin
Guest
 
Posts: n/a
Default [SI-LIST] Re: Altera PDN Tool

Joel:
This is good that you made light of this concern. A
simulator/calculator/spreadsheet is only as good as the understanding of its
limitations, where it is not valid. A good thing for Altera, would be to
include notes to such effect that you do not assume anything. In your case,
you validated what you believe to be inconsistent, which makes it no longer
an assumption. I do actually use their tool. It's simple but fairly
powerful, certainly quite useful.

Very good Joel.

Altera???

On Mon, Jul 20, 2009 at 5:17 PM, Joel Brown <joel (AT) zmicro (DOT) com> wrote:

> I have been playing around with the Altera PDN tool.
> When I look at the ESR and ESL values on the Library page it seems the
> values match very closely with AVX SpiCap3 which makes me think that is
> were
> the values came from.
>
> When I used Kemet's spice program I get values that are quite different..
> One
> which stood out was an ESL of 1.9nh for a .01uF 0402 capacitor.
>
> So it makes me wonder if I use the values in the Altera library if the
> results are going to be anywhere close to reality especially if we are
> buying capacitors from Kemet or another vendor.
>
> I am assuming the ESL values in the Altera library don't include the
> mounting inductance since they model that separately.
>
> Is there any information comparing ESL from different capacitor vendors for
> 0402 or any other size capacitors?
>
>
>
> Thanks - Joel
>
>
>
>
>
>
>
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
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>
>



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  #4 (permalink)  
Old 07-21-2009, 07:03 PM
Gumaste, Vijaylaxmi
Guest
 
Posts: n/a
Default [SI-LIST] PCB solder current carrying capacity

Hi,



I want to determine current carrying capacity of solder pads - effect of solder material/ land-pad size for very high current applications (>5A-10A per solder pad)



I can use IPC spec to design appropriate metal layer trace widths/thickness for a required temp rise.

However, I am looking at options to estimate/calculate/simulate current carrying capacity for solder pads.





-Vijaya.

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  #5 (permalink)  
Old 07-22-2009, 12:12 AM
Doug Brooks
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB solder current carrying capacity

In one of the articles on our web site re current carrying capacity
of traces, we include this observation (which is approximate).
The resistivity of solder (depending on its composition) is
approximately ten times higher than that for copper. Thus, you can
think of the trace (pad) and solder as being two conductors in
parallel --- one with 10x the resistance of the other (assuming
similar widths and thicknesses.)

On standard traces, we tell our customers to ignore the current
carrying capacity of the solder and just consider the copper itself.
Then it is determined just by the cross-sectional area of the copper.

Doug Brooks
UltraCAD
http://www.ultracad.com




At 11:03 AM 7/21/2009, Gumaste, Vijaylaxmi wrote:

>Hi,
>
>
>
>I want to determine current carrying capacity of solder pads -
>effect of solder material/ land-pad size for very high current
>applications (>5A-10A per solder pad)
>
>
>
>I can use IPC spec to design appropriate metal layer trace
>widths/thickness for a required temp rise.
>
>However, I am looking at options to estimate/calculate/simulate
>current carrying capacity for solder pads.
>
>
>
>
>
>-Vijaya.
>
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
>or to administer your membership from a web page, go to:
>http://www.freelists.org/webpage/si-list
>
>For help:
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>
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>


Check out our resources at http://www.ultracad.com

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  #6 (permalink)  
Old 07-22-2009, 12:36 AM
Scott McMorrow
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB solder current carrying capacity

Vijaya
If you're trying to push thermal limits, you'll want to read this paper.

http://ieeexplore.ieee.org/xpl/freea...number=1320488

Doug Brooks wrote:
> In one of the articles on our web site re current carrying capacity
> of traces, we include this observation (which is approximate).
> The resistivity of solder (depending on its composition) is
> approximately ten times higher than that for copper. Thus, you can
> think of the trace (pad) and solder as being two conductors in
> parallel --- one with 10x the resistance of the other (assuming
> similar widths and thicknesses.)
>
> On standard traces, we tell our customers to ignore the current
> carrying capacity of the solder and just consider the copper itself.
> Then it is determined just by the cross-sectional area of the copper.
>
> Doug Brooks
> UltraCAD
> http://www.ultracad.com
>
>
>
>
> At 11:03 AM 7/21/2009, Gumaste, Vijaylaxmi wrote:
>
>
>> Hi,
>>
>>
>>
>> I want to determine current carrying capacity of solder pads -
>> effect of solder material/ land-pad size for very high current
>> applications (>5A-10A per solder pad)
>>
>>
>>
>> I can use IPC spec to design appropriate metal layer trace
>> widths/thickness for a required temp rise.
>>
>> However, I am looking at options to estimate/calculate/simulate
>> current carrying capacity for solder pads.
>>
>>
>>
>>
>>
>> -Vijaya.
>>
>> ------------------------------------------------------------------
>> To unsubscribe from si-list:
>> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>>
>> or to administer your membership from a web page, go to:
>> http://www.freelists.org/webpage/si-list
>>
>> For help:
>> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>>
>>
>> List technical documents are available at:
>> http://www.si-list.net
>>
>> List archives are viewable at:
>> http://www.freelists.org/archives/si-list
>> or at our remote archives:
>> http://groups.yahoo.com/group/si-list/messages
>> Old (prior to June 6, 2001) list archives are viewable at:
>> http://www.qsl.net/wb6tpu
>>
>>

>
> Check out our resources at http://www.ultracad.com
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
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>
> For help:
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>
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> Old (prior to June 6, 2001) list archives are viewable at:
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>
>
>


--
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC



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  #7 (permalink)  
Old 07-22-2009, 12:40 AM
Gumaste, Vijaylaxmi
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB solder current carrying capacity

Have you seen any electro-migration failures at the interface between Cu-pad to solder intermetallics?



-Vijaya



-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org] On Behalf Of Doug Brooks
Sent: Tuesday, July 21, 2009 4:13 PM
To: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB solder current carrying capacity



In one of the articles on our web site re current carrying capacity

of traces, we include this observation (which is approximate).

The resistivity of solder (depending on its composition) is

approximately ten times higher than that for copper. Thus, you can

think of the trace (pad) and solder as being two conductors in

parallel --- one with 10x the resistance of the other (assuming

similar widths and thicknesses.)



On standard traces, we tell our customers to ignore the current

carrying capacity of the solder and just consider the copper itself.

Then it is determined just by the cross-sectional area of the copper.



Doug Brooks

UltraCAD

http://www.ultracad.com









At 11:03 AM 7/21/2009, Gumaste, Vijaylaxmi wrote:



>Hi,


>


>


>


>I want to determine current carrying capacity of solder pads -


>effect of solder material/ land-pad size for very high current


>applications (>5A-10A per solder pad)


>


>


>


>I can use IPC spec to design appropriate metal layer trace


>widths/thickness for a required temp rise.


>


>However, I am looking at options to estimate/calculate/simulate


>current carrying capacity for solder pads.


>


>


>


>


>


>-Vijaya.


>


>------------------------------------------------------------------


>To unsubscribe from si-list:


>si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field


>


>or to administer your membership from a web page, go to:


>http://www.freelists.org/webpage/si-list


>


>For help:


>si-list-request (AT) freelists (DOT) org with 'help' in the Subject field


>


>


>List technical documents are available at:


> http://www.si-list.net


>


>List archives are viewable at:


> http://www.freelists.org/archives/si-list


>or at our remote archives:


> http://groups.yahoo.com/group/si-list/messages


>Old (prior to June 6, 2001) list archives are viewable at:


> http://www.qsl.net/wb6tpu


>




Check out our resources at http://www.ultracad.com



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  #8 (permalink)  
Old 07-22-2009, 12:48 AM
qazi
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB solder current carrying capacity

Doug,
I am somewhat confused about the parallel conductor thing for solders
(probably too late in the day). It is a series resistor (~10x) and then why
current carrying ability is not a concern?

-Qazi

-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org] On
Behalf Of Doug Brooks
Sent: Tuesday, July 21, 2009 4:13 PM
To: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB solder current carrying capacity

In one of the articles on our web site re current carrying capacity
of traces, we include this observation (which is approximate).
The resistivity of solder (depending on its composition) is
approximately ten times higher than that for copper. Thus, you can
think of the trace (pad) and solder as being two conductors in
parallel --- one with 10x the resistance of the other (assuming
similar widths and thicknesses.)

On standard traces, we tell our customers to ignore the current
carrying capacity of the solder and just consider the copper itself.
Then it is determined just by the cross-sectional area of the copper.

Doug Brooks
UltraCAD
http://www.ultracad.com




At 11:03 AM 7/21/2009, Gumaste, Vijaylaxmi wrote:

>Hi,
>
>
>
>I want to determine current carrying capacity of solder pads -
>effect of solder material/ land-pad size for very high current
>applications (>5A-10A per solder pad)
>
>
>
>I can use IPC spec to design appropriate metal layer trace
>widths/thickness for a required temp rise.
>
>However, I am looking at options to estimate/calculate/simulate
>current carrying capacity for solder pads.
>
>
>
>
>
>-Vijaya.
>
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
>or to administer your membership from a web page, go to:
>http://www.freelists.org/webpage/si-list
>
>For help:
>si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
>List technical documents are available at:
> http://www.si-list.net
>
>List archives are viewable at:
> http://www.freelists.org/archives/si-list
>or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
>Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>


Check out our resources at http://www.ultracad.com

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  #9 (permalink)  
Old 07-22-2009, 01:32 AM
Scott McMorrow
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB solder current carrying capacity

These slides discuss the issues with solder.
http://www.sematech.org/meetings/arc...003_10_Tu..pdf

On the pentium 4 package intel used a maximum current density of 3.3e4
A/cm2 and a maximum local temperature of 120C as their design target,
based on reliability studies.



Gumaste, Vijaylaxmi wrote:
> Have you seen any electro-migration failures at the interface between Cu-pad to solder intermetallics?
>
>
>
> -Vijaya
>
>
>
> -----Original Message-----
> From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org] On Behalf Of Doug Brooks
> Sent: Tuesday, July 21, 2009 4:13 PM
> To: si-list (AT) freelists (DOT) org
> Subject: [SI-LIST] Re: PCB solder current carrying capacity
>
>
>
> In one of the articles on our web site re current carrying capacity
>
> of traces, we include this observation (which is approximate).
>
> The resistivity of solder (depending on its composition) is
>
> approximately ten times higher than that for copper. Thus, you can
>
> think of the trace (pad) and solder as being two conductors in
>
> parallel --- one with 10x the resistance of the other (assuming
>
> similar widths and thicknesses.)
>
>
>
> On standard traces, we tell our customers to ignore the current
>
> carrying capacity of the solder and just consider the copper itself.
>
> Then it is determined just by the cross-sectional area of the copper.
>
>
>
> Doug Brooks
>
> UltraCAD
>
> http://www.ultracad.com
>
>
>
>
>
>
>
>
>
> At 11:03 AM 7/21/2009, Gumaste, Vijaylaxmi wrote:
>
>
>
>
>> Hi,
>>

>
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>
>
>
>
>
>
>> I want to determine current carrying capacity of solder pads -
>>

>
>
>> effect of solder material/ land-pad size for very high current
>>

>
>
>> applications (>5A-10A per solder pad)
>>

>
>
>
>
>
>
>
>
>> I can use IPC spec to design appropriate metal layer trace
>>

>
>
>> widths/thickness for a required temp rise.
>>

>
>
>
>
>> However, I am looking at options to estimate/calculate/simulate
>>

>
>
>> current carrying capacity for solder pads.
>>

>
>
>
>
>
>
>
>
>
>
>
>
>> -Vijaya.
>>

>
>
>
>
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  #10 (permalink)  
Old 07-22-2009, 06:46 PM
Allen Mayar/EXTON/USA/SALES/KEMET/US
Guest
 
Posts: n/a
Default [SI-LIST] Re: Altera PDN Tool

Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: quoted-printable
At one time, the industry accepted that ESL was constant with frequency,=20
but we now know that is not true. We did see that the inductance varied=20
with measuring the mounted capacitor as opposed to the fixtured component, =

and for the most of the manufacturers, the measurements are on mounted=20
components as this represents the use conditions.

In the higher capacitance structures, we've been able to see that=20
inductance decreases to some asymptotic level (depending on case size)=20
that we were not able to measure with lower values. Because of this,=20
where the manufacturer measures the ESL may also introduce additional=20
variance between their ratings for similar devices. Some measure the ESL=20
at self-resonance (higher ESLs as KEMET reports) and others measure well=20
above self-resonance"lower is better". If a manufacturer specifies an ESL =

for all capacitance values in a case size as constant, then they are=20
using the ESL well above self-resonance. There are cases where this is=20
true, and in their catalogs, they'll include Impedance versus Frequency=20
responses for multiple capacitance values. Based on the capacitance=20
value, and the self-resonance of the Impedance plot, the derived ESL does=20
not match the "claimed" ESL.

The fact is that both of these are incorrect. The ESL does decay from the =

self-resonant frequency to well above this frequency. The theory is that=20
at self-resonance, the current is spread fairly evenly through the height=20
of the chip, but as frequency increases, the loop compresses until the=20
current is compressed into a minimized loop in the component. The=20
discrepancies in low frequency ESL and high frequency ESL is greatest for=20
those components utilizing the full height of the chip for the electrodes=20
(higher capacitance).

Within the next six months, we will be introducing a variable ESL model=20
in our Spice program, concentrating on the higher capacitance values at=20
first. Attached is a layout of the model which incorporates an "RL"=20
circuit in place of a single, fixed "L" component which will simulate this =

decaying ESL. In lower frequencies the ESL is based on a summation of L1=20
through L4, but in higher frequencies, L1 and L2 are the only inductive=20
elements, with L1 representing the termination and pad inductances. The=20
parallel resonance is factored by L2 and C2, and a secondary series=20
resonance by L1 and C2. Instead of replacing the existing model, this=20
model may be optional to the existing model.


=20



From:
Leonard Dieguez <ldieguez (AT) altera (DOT) com>
To:
Joel Brown <joel (AT) zmicro (DOT) com>, "si-list (AT) freelists (DOT) org"=20
<si-list (AT) freelists (DOT) org>
Cc:
John Oh <JOH (AT) altera (DOT) com>
Date:
07/21/2009 01:35 PM
Subject:
[SI-LIST] Re: Altera PDN Tool
Sent by:
si-list-bounce (AT) freelists (DOT) org



Joel,

I'm not 100 % sure what manufacturer was used when those values where=20
input to the tool but probably AVX or Murata. The values do not represent=20
the mounting inductance since the tool calculates that depending on the=20
mounting style and dimensions that are input to the tool. You can also=20
change your library or use "user values" for ESL /ESR. As with any other=20
EDA tool Garbage in equals garbage out. So check the values for the caps=20
that you are actually using and also check things like the stack up=20
heights Via placement and diameters and trace widths.

Leonard Dieguez
High Speed IO Applications,
Altera Corporation
9330 Scranton Road, Suite 400
San Diego, CA 92121
ldieguez (AT) altera (DOT) com
858.202.3511 (office)
"There are two kinds of engineers - those who have signal integrity=20
problems, and those who will." - Eric Bogatin.


-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]=20
On Behalf Of Joel Brown
Sent: Monday, July 20, 2009 5:17 PM
To: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Altera PDN Tool

I have been playing around with the Altera PDN tool.
When I look at the ESR and ESL values on the Library page it seems the
values match very closely with AVX SpiCap3 which makes me think that is=20
were
the values came from.

When I used Kemet's spice program I get values that are quite different.=20
One
which stood out was an ESL of 1.9nh for a .01uF 0402 capacitor.

So it makes me wonder if I use the values in the Altera library if the
results are going to be anywhere close to reality especially if we are
buying capacitors from Kemet or another vendor.

I am assuming the ESL values in the Altera library don't include the
mounting inductance since they model that separately.

Is there any information comparing ESL from different capacitor vendors=20
for
0402 or any other size capacitors?



Thanks - Joel









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Confidentiality Notice.
This message may contain information that is confidential or otherwise=20
protected from disclosure. If you are not the intended recipient, you are=20
hereby notified that any use, disclosure, dissemination, distribution, or =

copying of this message, or any attachments, is strictly prohibited. If=20
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THIS CORRESPONDENCE CONTAINS CONFIDENTIAL INFORMATION OF KEMET ELECTRONICS =
CORPORATION AND ITS AFFILIATED COMPANIES. If you have received this e-mail=
and it was not intended for you, please let us know, and then delete it. =
We thank you for treating our confidential information in a courteous and p=
rofessional manner.

DISCLAIMER: Although we have taken reasonable steps to reduce risks agains=
t viruses, the reliability of this method of communication cannot be guaran=
teed. It can be intercepted, corrupted, or delayed, or it may arrive incom=
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