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  #1 (permalink)  
Old 03-02-2009, 05:25 AM
Guest
 
Posts: n/a
Default [SI-LIST] Advantages & Disadvantages of Flooding Vias??

Hi Gentleman,

Good Morning.
I am working on a dense Aerospace Cockpit Control Board and I want to
Flood all of my Vias as Vias Connecting to the Respective planes (Power
& Gnd) is not having good connectivity through the Thermal Spokes.
Flooding vias will help me gaining the required copper area for the
Circuit.
Via size used is .015 Inch Drill\.025 Inch Pad.
Will this create any problem in the Component Assembling Process as some
of the heat may pass through the planes and thus PCB may undergo Bow &
Twist or expansion of the PCB.

Please put your expertise thoughts on it.

Thank you,
Regards,
Manatosh



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  #2 (permalink)  
Old 03-02-2009, 06:09 AM
steve weir
Guest
 
Posts: n/a
Default [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??

Thermal ties are appropriate when you want to limit the heat sinking,
such as with a TH component lead, where excessive heatsinking will make
reliable soldering and desoldering difficult to impossible. Continuous
pads are the norm for stitch vias.

Typical thermal ties cover a minimum of 180 degrees arc. For instance
if your antipads are 0.035" 0.015" ties would cover 185 degrees arc at
the outside of the antipad. Are you sure that thermals insert too much
resistance? If they do, I would be concerned about the current carrying
capacity of the via barrels.

Steve
ManatoshGBaidya (AT) Eaton (DOT) com wrote:
> Hi Gentleman,
>
> Good Morning.
> I am working on a dense Aerospace Cockpit Control Board and I want to
> Flood all of my Vias as Vias Connecting to the Respective planes (Power
> & Gnd) is not having good connectivity through the Thermal Spokes.
> Flooding vias will help me gaining the required copper area for the
> Circuit.
> Via size used is .015 Inch Drill\.025 Inch Pad.
> Will this create any problem in the Component Assembling Process as some
> of the heat may pass through the planes and thus PCB may undergo Bow &
> Twist or expansion of the PCB.
>
> Please put your expertise thoughts on it.
>
> Thank you,
> Regards,
> Manatosh
>
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of Teraspeed Consulting Group LLC
------------------------------------------------------------------------------------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting Group LLC

------------------------------------------------------------------
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Old (prior to June 6, 2001) list archives are viewable at:
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Reply With Quote
  #3 (permalink)  
Old 03-02-2009, 06:30 AM
Guest
 
Posts: n/a
Default [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??

Hi Steve,
Thank you for your prompt reply.
Here I am only concerned much about the Via through holes from Top to
Bottom Layer. I using almost all of the SMD Components except few
Through Hole Inductors & DC-DC Converter.
You are right,Thermals create a amount of Resistance but is okay to me.
I am not using Vias for Testing also. I am adding separate Test Pads.All
of my vias are closed with Mask.
If I flood all of my vias rather than using thermal, will it cause any
problem in the Assembling process. Will it pick heat through vias and
circulate the same heat in all the plane layers due to flooding (Full
contact with the Plane).Here Heat dissipation will not happen.Heat will
spread out in all the Plane Layers.

FYI.. Via size is small i.e 015 Inch Drill\.025 Inch Pad.

Total amount of current I have right now is 1Amp.

Pls advise me thereby

Regards,

Manatosh


-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On Behalf Of steve weir
Sent: Monday, March 02, 2009 11:40 AM
To: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??

Thermal ties are appropriate when you want to limit the heat sinking,
such as with a TH component lead, where excessive heatsinking will make
reliable soldering and desoldering difficult to impossible. Continuous
pads are the norm for stitch vias.

Typical thermal ties cover a minimum of 180 degrees arc. For instance
if your antipads are 0.035" 0.015" ties would cover 185 degrees arc at
the outside of the antipad. Are you sure that thermals insert too much
resistance? If they do, I would be concerned about the current carrying
capacity of the via barrels.

Steve
ManatoshGBaidya (AT) Eaton (DOT) com wrote:
> Hi Gentleman,
>
> Good Morning.
> I am working on a dense Aerospace Cockpit Control Board and I want to
> Flood all of my Vias as Vias Connecting to the Respective planes
> (Power & Gnd) is not having good connectivity through the Thermal

Spokes.
> Flooding vias will help me gaining the required copper area for the
> Circuit.
> Via size used is .015 Inch Drill\.025 Inch Pad.
> Will this create any problem in the Component Assembling Process as
> some of the heat may pass through the planes and thus PCB may undergo
> Bow & Twist or expansion of the PCB.
>
> Please put your expertise thoughts on it.
>
> Thank you,
> Regards,
> Manatosh
>
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property
of Teraspeed Consulting Group LLC
------------------------------------------------------------------------
------------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting
Group LLC

------------------------------------------------------------------
To unsubscribe from si-list:
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For help:
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List archives are viewable at:
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Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu





------------------------------------------------------------------
To unsubscribe from si-list:
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or to administer your membership from a web page, go to:
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For help:
si-list-request (AT) freelists (DOT) org with 'help' in the Subject field


List technical documents are available at:
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List archives are viewable at:
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or at our remote archives:
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Old (prior to June 6, 2001) list archives are viewable at:
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Reply With Quote
  #4 (permalink)  
Old 03-02-2009, 07:56 AM
steve weir
Guest
 
Posts: n/a
Default [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??

The reason for thermals is to facilitate TH solder / desolder. SMD
parts usually have no problem provided surface thermal relief to solder
pads is included as necessary. With a TH part it is different.
Intimate contact between a TH lead and a big planar heat sink inside the
PCB multiplies the amount of heat power needed to bring the lead end up
to soldering / desoldering temperature.

Steve.
ManatoshGBaidya (AT) Eaton (DOT) com wrote:
> Hi Steve,
> Thank you for your prompt reply.
> Here I am only concerned much about the Via through holes from Top to
> Bottom Layer. I using almost all of the SMD Components except few
> Through Hole Inductors & DC-DC Converter.
> You are right,Thermals create a amount of Resistance but is okay to me.
> I am not using Vias for Testing also. I am adding separate Test Pads.All
> of my vias are closed with Mask.
> If I flood all of my vias rather than using thermal, will it cause any
> problem in the Assembling process. Will it pick heat through vias and
> circulate the same heat in all the plane layers due to flooding (Full
> contact with the Plane).Here Heat dissipation will not happen.Heat will
> spread out in all the Plane Layers.
>
> FYI.. Via size is small i.e 015 Inch Drill\.025 Inch Pad.
>
> Total amount of current I have right now is 1Amp.
>
> Pls advise me thereby
>
> Regards,
>
> Manatosh
>
>
> -----Original Message-----
> From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
> On Behalf Of steve weir
> Sent: Monday, March 02, 2009 11:40 AM
> To: si-list (AT) freelists (DOT) org
> Subject: [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??
>
> Thermal ties are appropriate when you want to limit the heat sinking,
> such as with a TH component lead, where excessive heatsinking will make
> reliable soldering and desoldering difficult to impossible. Continuous
> pads are the norm for stitch vias.
>
> Typical thermal ties cover a minimum of 180 degrees arc. For instance
> if your antipads are 0.035" 0.015" ties would cover 185 degrees arc at
> the outside of the antipad. Are you sure that thermals insert too much
> resistance? If they do, I would be concerned about the current carrying
> capacity of the via barrels.
>
> Steve
> ManatoshGBaidya (AT) Eaton (DOT) com wrote:
>
>> Hi Gentleman,
>>
>> Good Morning.
>> I am working on a dense Aerospace Cockpit Control Board and I want to
>> Flood all of my Vias as Vias Connecting to the Respective planes
>> (Power & Gnd) is not having good connectivity through the Thermal
>>

> Spokes.
>
>> Flooding vias will help me gaining the required copper area for the
>> Circuit.
>> Via size used is .015 Inch Drill\.025 Inch Pad.
>> Will this create any problem in the Component Assembling Process as
>> some of the heat may pass through the planes and thus PCB may undergo
>> Bow & Twist or expansion of the PCB.
>>
>> Please put your expertise thoughts on it.
>>
>> Thank you,
>> Regards,
>> Manatosh
>>
>>
>>
>> ------------------------------------------------------------------
>> To unsubscribe from si-list:
>> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>>
>> or to administer your membership from a web page, go to:
>> http://www.freelists.org/webpage/si-list
>>
>> For help:
>> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>>
>>
>> List technical documents are available at:
>> http://www.si-list.net
>>
>> List archives are viewable at:
>> http://www.freelists.org/archives/si-list
>> or at our remote archives:
>> http://groups.yahoo.com/group/si-list/messages
>> Old (prior to June 6, 2001) list archives are viewable at:
>> http://www.qsl.net/wb6tpu
>>
>>
>>
>>
>>

>
>
> --
> Steve Weir
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
>
> California office
> (866) 675-4630 Business
> (707) 780-1951 Fax
>
> Main office
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> Oregon office
> (503) 430-1065 Business
> (503) 430-1285 Fax
>
> http://www.teraspeed.com
> This e-mail contains proprietary and confidential intellectual property
> of Teraspeed Consulting Group LLC
> ------------------------------------------------------------------------
> ------------------------------
> Teraspeed(R) is the registered service mark of Teraspeed Consulting
> Group LLC
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of Teraspeed Consulting Group LLC
------------------------------------------------------------------------------------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting Group LLC

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request (AT) freelists (DOT) org with 'help' in the Subject field


List technical documents are available at:
http://www.si-list.net

List archives are viewable at:
http://www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
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Reply With Quote
  #5 (permalink)  
Old 03-02-2009, 01:30 PM
Istvan Novak
Guest
 
Posts: n/a
Default [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??

Hi Manatosh,

If you design a cockpit control board, it does not sound like a home
hobby project, so you should
have ready access to the people who are going to fabricate and assemble
the board. The board
fabricator should comment on concerns they may have about board warping
and bowing, though
using thermal relief patterns or solid via hits probably will make very
little difference; symmetrical
stackup and equalizing the copper coverage in the layers are the primary
factors. If and where you
use only SMD parts, the thermal connection makes no difference in the
solderability of those parts.

However, if you cover the via openings at both ends with a solid polymer
solder mask, it most
probably will be blown away during the assembly process as the trapped
air expands. I dont think
that thermal-relief connections would help with this. So to me the
first question seems to be: why
would you want to cover the via openings: any special reason?

Regards,

Istvan Novak
SUN Microsystems


ManatoshGBaidya (AT) Eaton (DOT) com wrote:
> Hi Steve,
> Thank you for your prompt reply.
> Here I am only concerned much about the Via through holes from Top to
> Bottom Layer. I using almost all of the SMD Components except few
> Through Hole Inductors & DC-DC Converter.
> You are right,Thermals create a amount of Resistance but is okay to me.
> I am not using Vias for Testing also. I am adding separate Test Pads.All
> of my vias are closed with Mask.
> If I flood all of my vias rather than using thermal, will it cause any
> problem in the Assembling process. Will it pick heat through vias and
> circulate the same heat in all the plane layers due to flooding (Full
> contact with the Plane).Here Heat dissipation will not happen.Heat will
> spread out in all the Plane Layers.
>
> FYI.. Via size is small i.e 015 Inch Drill\.025 Inch Pad.
>
> Total amount of current I have right now is 1Amp.
>
> Pls advise me thereby
>
> Regards,
>
> Manatosh
>
>
> -----Original Message-----
> From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
> On Behalf Of steve weir
> Sent: Monday, March 02, 2009 11:40 AM
> To: si-list (AT) freelists (DOT) org
> Subject: [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??
>
> Thermal ties are appropriate when you want to limit the heat sinking,
> such as with a TH component lead, where excessive heatsinking will make
> reliable soldering and desoldering difficult to impossible. Continuous
> pads are the norm for stitch vias.
>
> Typical thermal ties cover a minimum of 180 degrees arc. For instance
> if your antipads are 0.035" 0.015" ties would cover 185 degrees arc at
> the outside of the antipad. Are you sure that thermals insert too much
> resistance? If they do, I would be concerned about the current carrying
> capacity of the via barrels.
>
> Steve
> ManatoshGBaidya (AT) Eaton (DOT) com wrote:
>
>> Hi Gentleman,
>>
>> Good Morning.
>> I am working on a dense Aerospace Cockpit Control Board and I want to
>> Flood all of my Vias as Vias Connecting to the Respective planes
>> (Power & Gnd) is not having good connectivity through the Thermal
>>

> Spokes.
>
>> Flooding vias will help me gaining the required copper area for the
>> Circuit.
>> Via size used is .015 Inch Drill\.025 Inch Pad.
>> Will this create any problem in the Component Assembling Process as
>> some of the heat may pass through the planes and thus PCB may undergo
>> Bow & Twist or expansion of the PCB.
>>
>> Please put your expertise thoughts on it.
>>
>> Thank you,
>> Regards,
>> Manatosh
>>
>>
>>
>> ------------------------------------------------------------------
>> To unsubscribe from si-list:
>> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>>
>> or to administer your membership from a web page, go to:
>> http://www.freelists.org/webpage/si-list
>>
>> For help:
>> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>>
>>
>> List technical documents are available at:
>> http://www.si-list.net
>>
>> List archives are viewable at:
>> http://www.freelists.org/archives/si-list
>> or at our remote archives:
>> http://groups.yahoo.com/group/si-list/messages
>> Old (prior to June 6, 2001) list archives are viewable at:
>> http://www.qsl.net/wb6tpu
>>
>>
>>
>>
>>

>
>
> --
> Steve Weir
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
>
> California office
> (866) 675-4630 Business
> (707) 780-1951 Fax
>
> Main office
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> Oregon office
> (503) 430-1065 Business
> (503) 430-1285 Fax
>
> http://www.teraspeed.com
> This e-mail contains proprietary and confidential intellectual property
> of Teraspeed Consulting Group LLC
> ------------------------------------------------------------------------
> ------------------------------
> Teraspeed(R) is the registered service mark of Teraspeed Consulting
> Group LLC
>
>


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request (AT) freelists (DOT) org with 'help' in the Subject field


List technical documents are available at:
http://www.si-list.net

List archives are viewable at:
http://www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Reply With Quote
  #6 (permalink)  
Old 03-02-2009, 03:19 PM
Richard Jungert
Guest
 
Posts: n/a
Default [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??

Manatosh.

One of the things you could do is use 2oz. copper. With 2 oz. copper you will have to make all your spacing checks with min 0.010" clearance. Because of the density of the board your doing this may or may not work, or you may be too far along to try this but 2 oz. copper but its great for thermal dissapation. 1.5 oz copper is also available last time I talked to fabricators.

From your message I think your making a thermal path.
If your building a thermal path, one thing I have done in the past is settup special vias for thermal dissapation. These special types of vias don't have thermal spokes and drill holes can be much larger to facilitate a good copper fill.

Having problems with the board warping you may want to think about how well balanced the copper routing is distributed from top to bottom layers. Too much copper on the top layers and then very few routes or planes on the bottom layers with cause your board to warp towards the layers with excessive copper. Try to distribute your routing and copper planes evenly from top to bottom of your design. Another thing one can do is ask your fabricator to add thieving on layers where copper is sparse. From my experience the fabricator will do this as an added bonus. Always put this request in your fab notes and your on your way.

Balance is always a good thing when designing boards and circuits.

Good luck.

Richard Jungert
http://www.rjungert.com

170 board designs
3D EM Simulations to 50Ghz with Sonnet
S parameter evaluations
2 US patents

















> Date: Sun, 1 Mar 2009 22:09:47 -0800
> From: weirsi (AT) ipblox (DOT) com
> To: si-list (AT) freelists (DOT) org
> Subject: [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??
>
> Thermal ties are appropriate when you want to limit the heat sinking,
> such as with a TH component lead, where excessive heatsinking will make
> reliable soldering and desoldering difficult to impossible. Continuous
> pads are the norm for stitch vias.
>
> Typical thermal ties cover a minimum of 180 degrees arc. For instance
> if your antipads are 0.035" 0.015" ties would cover 185 degrees arc at
> the outside of the antipad. Are you sure that thermals insert too much
> resistance? If they do, I would be concerned about the current carrying
> capacity of the via barrels.
>
> Steve
> ManatoshGBaidya (AT) Eaton (DOT) com wrote:
> > Hi Gentleman,
> >
> > Good Morning.
> > I am working on a dense Aerospace Cockpit Control Board and I want to
> > Flood all of my Vias as Vias Connecting to the Respective planes (Power
> > & Gnd) is not having good connectivity through the Thermal Spokes.
> > Flooding vias will help me gaining the required copper area for the
> > Circuit.
> > Via size used is .015 Inch Drill\.025 Inch Pad.
> > Will this create any problem in the Component Assembling Process as some
> > of the heat may pass through the planes and thus PCB may undergo Bow &
> > Twist or expansion of the PCB.
> >
> > Please put your expertise thoughts on it.
> >
> > Thank you,
> > Regards,
> > Manatosh
> >
> >
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
> >
> > or to administer your membership from a web page, go to:
> > http://www.freelists.org/webpage/si-list
> >
> > For help:
> > si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
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> >
> > List technical documents are available at:
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> > http://www.freelists.org/archives/si-list
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> > http://www.qsl.net/wb6tpu
> >
> >
> >
> >

>
>
> --
> Steve Weir
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
>
> California office
> (866) 675-4630 Business
> (707) 780-1951 Fax
>
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  #7 (permalink)  
Old 03-02-2009, 03:28 PM
Jack Olson
Guest
 
Posts: n/a
Default [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??

You don't have anything to worry about.
The only reason for thermal relief is to reduce the amount of heat needed
for soldering/desoldering.

Vias aren't considered soldered connections, and many designers flood them
One of the only reasons for not flooding them is that the spoked connections
are easier to see in
plots and gerber data (flooded connections are difficult to "see").

Lamination and Soldering temperatures are much higher than your normal
operating temperature
(or else you have a bad design!) so any bow and twist will happen at the
extremes, not during normal operation. In other words, you'll see it before
it ever gets used in the field.
If it doesn't warp during assembly, it won't warp later on.

Heat will flow through your planes regardless, and nothing about vias
contributes to bow and twist.
As a matter of fact, getting more heat onto the planes will REDUCE your via
barrel stress
Jack


..
On Sun, Mar 1, 2009 at 11:25 PM, <ManatoshGBaidya (AT) eaton (DOT) com> wrote:

> Hi Gentleman,
>
> Good Morning.
> I am working on a dense Aerospace Cockpit Control Board and I want to
> Flood all of my Vias as Vias Connecting to the Respective planes (Power
> & Gnd) is not having good connectivity through the Thermal Spokes.
> Flooding vias will help me gaining the required copper area for the
> Circuit.
> Via size used is .015 Inch Drill\.025 Inch Pad.
> Will this create any problem in the Component Assembling Process as some
> of the heat may pass through the planes and thus PCB may undergo Bow &
> Twist or expansion of the PCB.
>
> Please put your expertise thoughts on it.
>
> Thank you,
> Regards,
> Manatosh
>
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>



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  #8 (permalink)  
Old 03-02-2009, 04:45 PM
Stefan Milnor
Guest
 
Posts: n/a
Default [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??

I agree with the advice given by Jack below.

Regarding not being able to "see" the vias in the Gerbers, I usually overlay the drill drawing on the Gerbers to make sure the plane connection vias are showing up where I think they should be, and do a spot check.

________________________________

From: si-list-bounce (AT) freelists (DOT) org on behalf of Jack Olson
Sent: Mon 3/2/2009 7:28 AM
To: ManatoshGBaidya (AT) eaton (DOT) com
Cc: eric (AT) bethesignal (DOT) com; istvan.novak (AT) att (DOT) net; si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??



You don't have anything to worry about.
The only reason for thermal relief is to reduce the amount of heat needed
for soldering/desoldering.

Vias aren't considered soldered connections, and many designers flood them
One of the only reasons for not flooding them is that the spoked connections
are easier to see in
plots and gerber data (flooded connections are difficult to "see").

Lamination and Soldering temperatures are much higher than your normal
operating temperature
(or else you have a bad design!) so any bow and twist will happen at the
extremes, not during normal operation. In other words, you'll see it before
it ever gets used in the field.
If it doesn't warp during assembly, it won't warp later on.

Heat will flow through your planes regardless, and nothing about vias
contributes to bow and twist.
As a matter of fact, getting more heat onto the planes will REDUCE your via
barrel stress
Jack


..
On Sun, Mar 1, 2009 at 11:25 PM, <ManatoshGBaidya (AT) eaton (DOT) com> wrote:

> Hi Gentleman,
>
> Good Morning.
> I am working on a dense Aerospace Cockpit Control Board and I want to
> Flood all of my Vias as Vias Connecting to the Respective planes (Power
> & Gnd) is not having good connectivity through the Thermal Spokes.
> Flooding vias will help me gaining the required copper area for the
> Circuit.
> Via size used is .015 Inch Drill\.025 Inch Pad.
> Will this create any problem in the Component Assembling Process as some
> of the heat may pass through the planes and thus PCB may undergo Bow &
> Twist or expansion of the PCB.
>
> Please put your expertise thoughts on it.
>
> Thank you,
> Regards,
> Manatosh
>
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>



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The information contained in this document is CONFIDENTIAL and property of Kontron. Any unauthorized review, use, disclosure or distribution is prohibited without express written consent of Kontron. If you are not the intended recipient, please contact the sender and destroy all copies of the original message and enclosed attachments.

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Reply With Quote
  #9 (permalink)  
Old 03-02-2009, 04:54 PM
Richard Jungert
Guest
 
Posts: n/a
Default [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??

Via's will show up in the gerber files just fine If you use the CAM350 tool to view them. I think that depends on the tool.

Richard Jungert

> Subject: [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??
> Date: Mon, 2 Mar 2009 08:45:17 -0800
> From: stefan.milnor (AT) us (DOT) kontron.com
> To: pcbjack (AT) gmail (DOT) com; ManatoshGBaidya (AT) eaton (DOT) com
> CC: eric (AT) bethesignal (DOT) com; istvan.novak (AT) att (DOT) net; si-list (AT) freelists (DOT) org
>
> I agree with the advice given by Jack below.
>
> Regarding not being able to "see" the vias in the Gerbers, I usually overlay the drill drawing on the Gerbers to make sure the plane connection vias are showing up where I think they should be, and do a spot check.
>
> ________________________________
>
> From: si-list-bounce (AT) freelists (DOT) org on behalf of Jack Olson
> Sent: Mon 3/2/2009 7:28 AM
> To: ManatoshGBaidya (AT) eaton (DOT) com
> Cc: eric (AT) bethesignal (DOT) com; istvan.novak (AT) att (DOT) net; si-list (AT) freelists (DOT) org
> Subject: [SI-LIST] Re: Advantages & Disadvantages of Flooding Vias??
>
>
>
> You don't have anything to worry about.
> The only reason for thermal relief is to reduce the amount of heat needed
> for soldering/desoldering.
>
> Vias aren't considered soldered connections, and many designers flood them
> One of the only reasons for not flooding them is that the spoked connections
> are easier to see in
> plots and gerber data (flooded connections are difficult to "see").
>
> Lamination and Soldering temperatures are much higher than your normal
> operating temperature
> (or else you have a bad design!) so any bow and twist will happen at the
> extremes, not during normal operation. In other words, you'll see it before
> it ever gets used in the field.
> If it doesn't warp during assembly, it won't warp later on.
>
> Heat will flow through your planes regardless, and nothing about vias
> contributes to bow and twist.
> As a matter of fact, getting more heat onto the planes will REDUCE your via
> barrel stress
> Jack
>
>
> .
> On Sun, Mar 1, 2009 at 11:25 PM, <ManatoshGBaidya (AT) eaton (DOT) com> wrote:
>
> > Hi Gentleman,
> >
> > Good Morning.
> > I am working on a dense Aerospace Cockpit Control Board and I want to
> > Flood all of my Vias as Vias Connecting to the Respective planes (Power
> > & Gnd) is not having good connectivity through the Thermal Spokes.
> > Flooding vias will help me gaining the required copper area for the
> > Circuit.
> > Via size used is .015 Inch Drill\.025 Inch Pad.
> > Will this create any problem in the Component Assembling Process as some
> > of the heat may pass through the planes and thus PCB may undergo Bow &
> > Twist or expansion of the PCB.
> >
> > Please put your expertise thoughts on it.
> >
> > Thank you,
> > Regards,
> > Manatosh
> >
> >
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
> >
> > or to administer your membership from a web page, go to:
> > http://www.freelists.org/webpage/si-list
> >
> > For help:
> > si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
> >
> >
> > List technical documents are available at:
> > http://www.si-list.net
> >
> > List archives are viewable at:
> > http://www.freelists.org/archives/si-list
> > or at our remote archives:
> > http://groups.yahoo.com/group/si-list/messages
> > Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> >
> >
> >

>
>
> ------------------------------------------------------------------
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>
>
>
>
>
> The information contained in this document is CONFIDENTIAL and property of Kontron. Any unauthorized review, use, disclosure or distribution is prohibited without express written consent of Kontron. If you are not the intended recipient, please contact the sender and destroy all copies of the original message and enclosed attachments.
>
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  #10 (permalink)  
Old 05-11-2009, 04:15 PM
QU Perry
Guest
 
Posts: n/a
Default [SI-LIST] PCB modelling wizard ?

Hi,

I wonder how everyone here creates the model when you try to do a 3D EM
simulation of PCB related features, do you:

1. manually create 3D model using the modeler that comes with the tool;
2. Use the interface tool provided by EM tool vendor to link to PCB or
mechanical CAD tool;

I always used option 1 for the following reasons:
1. only include features I need so make the model clean and small;
2. be able to parameterize and do what if analysis;
3. such 3D simulation is usually done in prelayout stage to explore
design space so no board file is available.

However, I get increasingly tired of doing this as it's a very time
consuming process. It's no fun to create multi layer PCB and all small
features such as pads, vias, traces, etc., manually, and each design
has something different which makes model reuse very difficult.

Was hoping for some kind of wizard tool to let me e.g. create
multi-layer PCB stackup, define via (pads, antipad etc.) using text
based dimensions and have the modeler create a PCB model automatically,
and I can add unique features/structures on top of that. That should
save a lot of time. Unfortunately not many vendors have that option or
interested in implementing them (currently using CST Microwave Studio).
I'm aware that Simberor has some of the capability described above but
then we can't afford getting every new tool in the market.

Regards

Perry

=======================================

Perry Qu

IPD Design & Qualification, Alcatel-Lucent Canada Inc.

600 March Road, Ottawa ON, K2K 2E6, Canada

DID: 613-7846720 Fax: 613-5993642

Email: perry.qu (AT) alcatel-lucent (DOT) com

=======================================

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  #11 (permalink)  
Old 05-11-2009, 05:23 PM
steve weir
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB modelling wizard ?

Perry, scripts are your friend here.

Best Regards,


Steve.
QU Perry wrote:
> Hi,
>
> I wonder how everyone here creates the model when you try to do a 3D EM
> simulation of PCB related features, do you:
>
> 1. manually create 3D model using the modeler that comes with the tool;
> 2. Use the interface tool provided by EM tool vendor to link to PCB or
> mechanical CAD tool;
>
> I always used option 1 for the following reasons:
> 1. only include features I need so make the model clean and small;
> 2. be able to parameterize and do what if analysis;
> 3. such 3D simulation is usually done in prelayout stage to explore
> design space so no board file is available.
>
> However, I get increasingly tired of doing this as it's a very time
> consuming process. It's no fun to create multi layer PCB and all small
> features such as pads, vias, traces, etc., manually, and each design
> has something different which makes model reuse very difficult.
>
> Was hoping for some kind of wizard tool to let me e.g. create
> multi-layer PCB stackup, define via (pads, antipad etc.) using text
> based dimensions and have the modeler create a PCB model automatically,
> and I can add unique features/structures on top of that. That should
> save a lot of time. Unfortunately not many vendors have that option or
> interested in implementing them (currently using CST Microwave Studio).
> I'm aware that Simberor has some of the capability described above but
> then we can't afford getting every new tool in the market.
>
> Regards
>
> Perry
>
> =======================================
>
> Perry Qu
>
> IPD Design & Qualification, Alcatel-Lucent Canada Inc.
>
> 600 March Road, Ottawa ON, K2K 2E6, Canada
>
> DID: 613-7846720 Fax: 613-5993642
>
> Email: perry.qu (AT) alcatel-lucent (DOT) com
>
> =======================================
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
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>
> For help:
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> List technical documents are available at:
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> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

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(503) 430-1285 Fax

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This e-mail contains proprietary and confidential intellectual property of Teraspeed Consulting Group LLC
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  #12 (permalink)  
Old 05-11-2009, 05:58 PM
Aubrey Sparkman
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB modelling wizard ?

Perry,

I agree that scripts are certainly the way to go if you do LOTS of 3D
modeling on a continual basis. For others who 3D modeling only at certain
points in a design cycle, it may be faster to use the interface tool. Even
for the pre-layout stage (and perhaps because I have some experience with
Allegro), I find it easier to setup a board and draw the desired geometry in
Allegro and then transfer it to the 3D tool than to setup a board and draw
the geometries in the 3D tool. For the post-layout correlation cases, it's
easy to delete unwanted geometries in Allegro and transfer the remainder.
Transfer to Momentum is very easy; transfer via Alinks to HFSS or Q3d has a
couple of bugs you need to watch out for but can be made to work. In any
case, you can convert specific parts of the design to parameterized parts
after the transfer.

For your specific needs, you should consider the script development as an
investment and see which way wins for overall productivity.


Aubrey Sparkman
Aubrey.K.Sparkman (AT) ieee (DOT) org

-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org] On
Behalf Of steve weir
Sent: Monday, May 11, 2009 11:23 AM
To: QU Perry
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Perry, scripts are your friend here.

Best Regards,


Steve.
QU Perry wrote:
> Hi,
>
> I wonder how everyone here creates the model when you try to do a 3D
> EM simulation of PCB related features, do you:
>
> 1. manually create 3D model using the modeler that comes with the
> tool; 2. Use the interface tool provided by EM tool vendor to link to
> PCB or mechanical CAD tool;
>
> I always used option 1 for the following reasons:
> 1. only include features I need so make the model clean and small; 2.
> be able to parameterize and do what if analysis; 3. such 3D simulation
> is usually done in prelayout stage to explore design space so no board
> file is available.
>
> However, I get increasingly tired of doing this as it's a very time
> consuming process. It's no fun to create multi layer PCB and all small
> features such as pads, vias, traces, etc., manually, and each design
> has something different which makes model reuse very difficult.
>
> Was hoping for some kind of wizard tool to let me e.g. create
> multi-layer PCB stackup, define via (pads, antipad etc.) using text
> based dimensions and have the modeler create a PCB model
> automatically, and I can add unique features/structures on top of
> that. That should save a lot of time. Unfortunately not many vendors
> have that option or interested in implementing them (currently using CST

Microwave Studio).
> I'm aware that Simberor has some of the capability described above but
> then we can't afford getting every new tool in the market.
>
> Regards
>
> Perry
>
> =======================================
>
> Perry Qu
>
> IPD Design & Qualification, Alcatel-Lucent Canada Inc.
>
> 600 March Road, Ottawa ON, K2K 2E6, Canada
>
> DID: 613-7846720 Fax: 613-5993642
>
> Email: perry.qu (AT) alcatel-lucent (DOT) com
>
> =======================================
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
Teraspeed Consulting Group LLC
----------------------------------------------------------------------------
--------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting Group
LLC

------------------------------------------------------------------
To unsubscribe from si-list:
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Reply With Quote
  #13 (permalink)  
Old 05-11-2009, 06:08 PM
QU Perry
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB modelling wizard ?

Thanks, Aubrey, Steve.

I guess we need to invest considerable amount of time and effort to get
the scripts done, and I was thinking since such feature are widely
useful for many EM tool users, why can't they do this as this is their
strength ?

In the meanwhile, I will look into the allegro link you mentioned. It's
not as straightforward but should save me some time.

Regards

Perry

=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu (AT) alcatel-lucent (DOT) com
=======================================

-----Original Message-----
From: Aubrey Sparkman [mailto:asparkman (AT) austin (DOT) rr.com]
Sent: Monday, May 11, 2009 12:58 PM
To: 'steve weir'; QU Perry
Cc: si-list (AT) freelists (DOT) org
Subject: RE: [SI-LIST] Re: PCB modelling wizard ?

Perry,

I agree that scripts are certainly the way to go if you do LOTS of 3D
modeling on a continual basis. For others who 3D modeling only at
certain
points in a design cycle, it may be faster to use the interface tool.
Even
for the pre-layout stage (and perhaps because I have some experience
with
Allegro), I find it easier to setup a board and draw the desired
geometry in
Allegro and then transfer it to the 3D tool than to setup a board and
draw
the geometries in the 3D tool. For the post-layout correlation cases,
it's
easy to delete unwanted geometries in Allegro and transfer the
remainder.
Transfer to Momentum is very easy; transfer via Alinks to HFSS or Q3d
has a
couple of bugs you need to watch out for but can be made to work. In
any
case, you can convert specific parts of the design to parameterized
parts
after the transfer.

For your specific needs, you should consider the script development as
an
investment and see which way wins for overall productivity.


Aubrey Sparkman
Aubrey.K.Sparkman (AT) ieee (DOT) org

-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On
Behalf Of steve weir
Sent: Monday, May 11, 2009 11:23 AM
To: QU Perry
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Perry, scripts are your friend here.

Best Regards,


Steve.
QU Perry wrote:
> Hi,
>
> I wonder how everyone here creates the model when you try to do a 3D
> EM simulation of PCB related features, do you:
>
> 1. manually create 3D model using the modeler that comes with the
> tool; 2. Use the interface tool provided by EM tool vendor to link to
> PCB or mechanical CAD tool;
>
> I always used option 1 for the following reasons:
> 1. only include features I need so make the model clean and small; 2.
> be able to parameterize and do what if analysis; 3. such 3D simulation


> is usually done in prelayout stage to explore design space so no board


> file is available.
>
> However, I get increasingly tired of doing this as it's a very time
> consuming process. It's no fun to create multi layer PCB and all small
> features such as pads, vias, traces, etc., manually, and each design
> has something different which makes model reuse very difficult.
>
> Was hoping for some kind of wizard tool to let me e.g. create
> multi-layer PCB stackup, define via (pads, antipad etc.) using text
> based dimensions and have the modeler create a PCB model
> automatically, and I can add unique features/structures on top of
> that. That should save a lot of time. Unfortunately not many vendors
> have that option or interested in implementing them (currently using

CST
Microwave Studio).
> I'm aware that Simberor has some of the capability described above but


> then we can't afford getting every new tool in the market.
>
> Regards
>
> Perry
>
> =======================================
>
> Perry Qu
>
> IPD Design & Qualification, Alcatel-Lucent Canada Inc.
>
> 600 March Road, Ottawa ON, K2K 2E6, Canada
>
> DID: 613-7846720 Fax: 613-5993642
>
> Email: perry.qu (AT) alcatel-lucent (DOT) com
>
> =======================================
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property
of
Teraspeed Consulting Group LLC
------------------------------------------------------------------------
----
--------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting
Group
LLC

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
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For help:
si-list-request (AT) freelists (DOT) org with 'help' in the Subject field


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List archives are viewable at:
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or at our remote archives:
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Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu




------------------------------------------------------------------
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or to administer your membership from a web page, go to:
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For help:
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Old (prior to June 6, 2001) list archives are viewable at:
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Reply With Quote
  #14 (permalink)  
Old 05-11-2009, 08:52 PM
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB modelling wizard ?

Perry,

Ansoft HFSS has a free "via wizard" which does exactly what you need.
You might want to get in touch with them if you do not already have it.

Best regards,
Vittal Balasubramanian
Sr. Signal Integrity Engineer
FCI USA, Inc.


-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On Behalf Of QU Perry
Sent: Monday, May 11, 2009 1:09 PM
To: Aubrey Sparkman; steve weir
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Thanks, Aubrey, Steve.

I guess we need to invest considerable amount of time and effort to get
the scripts done, and I was thinking since such feature are widely
useful for many EM tool users, why can't they do this as this is their
strength ?

In the meanwhile, I will look into the allegro link you mentioned. It's
not as straightforward but should save me some time.

Regards

Perry

=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu (AT) alcatel-lucent (DOT) com
=======================================

-----Original Message-----
From: Aubrey Sparkman [mailto:asparkman (AT) austin (DOT) rr.com]
Sent: Monday, May 11, 2009 12:58 PM
To: 'steve weir'; QU Perry
Cc: si-list (AT) freelists (DOT) org
Subject: RE: [SI-LIST] Re: PCB modelling wizard ?

Perry,

I agree that scripts are certainly the way to go if you do LOTS of 3D
modeling on a continual basis. For others who 3D modeling only at
certain
points in a design cycle, it may be faster to use the interface tool.
Even
for the pre-layout stage (and perhaps because I have some experience
with
Allegro), I find it easier to setup a board and draw the desired
geometry in
Allegro and then transfer it to the 3D tool than to setup a board and
draw
the geometries in the 3D tool. For the post-layout correlation cases,
it's
easy to delete unwanted geometries in Allegro and transfer the
remainder.
Transfer to Momentum is very easy; transfer via Alinks to HFSS or Q3d
has a
couple of bugs you need to watch out for but can be made to work. In
any
case, you can convert specific parts of the design to parameterized
parts
after the transfer.

For your specific needs, you should consider the script development as
an
investment and see which way wins for overall productivity.


Aubrey Sparkman
Aubrey.K.Sparkman (AT) ieee (DOT) org

-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On
Behalf Of steve weir
Sent: Monday, May 11, 2009 11:23 AM
To: QU Perry
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Perry, scripts are your friend here.

Best Regards,


Steve.
QU Perry wrote:
> Hi,
>
> I wonder how everyone here creates the model when you try to do a 3D
> EM simulation of PCB related features, do you:
>
> 1. manually create 3D model using the modeler that comes with the
> tool; 2. Use the interface tool provided by EM tool vendor to link to
> PCB or mechanical CAD tool;
>
> I always used option 1 for the following reasons:
> 1. only include features I need so make the model clean and small; 2.
> be able to parameterize and do what if analysis; 3. such 3D simulation


> is usually done in prelayout stage to explore design space so no board


> file is available.
>
> However, I get increasingly tired of doing this as it's a very time
> consuming process. It's no fun to create multi layer PCB and all small
> features such as pads, vias, traces, etc., manually, and each design
> has something different which makes model reuse very difficult.
>
> Was hoping for some kind of wizard tool to let me e.g. create
> multi-layer PCB stackup, define via (pads, antipad etc.) using text
> based dimensions and have the modeler create a PCB model
> automatically, and I can add unique features/structures on top of
> that. That should save a lot of time. Unfortunately not many vendors
> have that option or interested in implementing them (currently using

CST
Microwave Studio).
> I'm aware that Simberor has some of the capability described above but


> then we can't afford getting every new tool in the market.
>
> Regards
>
> Perry
>
> =======================================
>
> Perry Qu
>
> IPD Design & Qualification, Alcatel-Lucent Canada Inc.
>
> 600 March Road, Ottawa ON, K2K 2E6, Canada
>
> DID: 613-7846720 Fax: 613-5993642
>
> Email: perry.qu (AT) alcatel-lucent (DOT) com
>
> =======================================
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property
of
Teraspeed Consulting Group LLC
------------------------------------------------------------------------
----
--------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting
Group
LLC

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request (AT) freelists (DOT) org with 'help' in the Subject field


List technical documents are available at:
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List archives are viewable at:
http://www.freelists.org/archives/si-list
or at our remote archives:
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Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu




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Old (prior to June 6, 2001) list archives are viewable at:
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------------------------------------------------------------------
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or to administer your membership from a web page, go to:
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For help:
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Old (prior to June 6, 2001) list archives are viewable at:
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Reply With Quote
  #15 (permalink)  
Old 05-11-2009, 10:15 PM
Chris Herrick
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB modelling wizard ?

Hello all, as Vittal mentioned, a colleague and I wrote an HFSS Via
Wizard a few years back that's available free on the web. You can
download this from http://3DViaDesign.com. It has a simple GUI where the
user can enter stackup, padstack and via locations. The project is then
generated in HFSS ready solve. I parameterized most of the geometry so
the user can easily optimize the vias. There is no need to be a 3D
modeling expert.

This code is old but still works pretty well. I've recently updated and
enhanced the wizard and will be releasing a new version in the next few
weeks. If anyone has any questions or comments please email me offline.

Thanks,
Chris

-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On Behalf Of Vittal.Balasubramanian (AT) fci (DOT) com
Sent: Monday, May 11, 2009 12:53 PM
To: Perry.Qu (AT) alcatel-lucent (DOT) com; asparkman (AT) austin (DOT) rr.com;
weirsi (AT) ipblox (DOT) com
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Perry,

Ansoft HFSS has a free "via wizard" which does exactly what you need.
You might want to get in touch with them if you do not already have it.

Best regards,
Vittal Balasubramanian
Sr. Signal Integrity Engineer
FCI USA, Inc.


-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On Behalf Of QU Perry
Sent: Monday, May 11, 2009 1:09 PM
To: Aubrey Sparkman; steve weir
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Thanks, Aubrey, Steve.

I guess we need to invest considerable amount of time and effort to get
the scripts done, and I was thinking since such feature are widely
useful for many EM tool users, why can't they do this as this is their
strength ?

In the meanwhile, I will look into the allegro link you mentioned. It's
not as straightforward but should save me some time.

Regards

Perry

=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu (AT) alcatel-lucent (DOT) com
=======================================

-----Original Message-----
From: Aubrey Sparkman [mailto:asparkman (AT) austin (DOT) rr.com]
Sent: Monday, May 11, 2009 12:58 PM
To: 'steve weir'; QU Perry
Cc: si-list (AT) freelists (DOT) org
Subject: RE: [SI-LIST] Re: PCB modelling wizard ?

Perry,

I agree that scripts are certainly the way to go if you do LOTS of 3D
modeling on a continual basis. For others who 3D modeling only at
certain
points in a design cycle, it may be faster to use the interface tool.
Even
for the pre-layout stage (and perhaps because I have some experience
with
Allegro), I find it easier to setup a board and draw the desired
geometry in
Allegro and then transfer it to the 3D tool than to setup a board and
draw
the geometries in the 3D tool. For the post-layout correlation cases,
it's
easy to delete unwanted geometries in Allegro and transfer the
remainder.
Transfer to Momentum is very easy; transfer via Alinks to HFSS or Q3d
has a
couple of bugs you need to watch out for but can be made to work. In
any
case, you can convert specific parts of the design to parameterized
parts
after the transfer.

For your specific needs, you should consider the script development as
an
investment and see which way wins for overall productivity.


Aubrey Sparkman
Aubrey.K.Sparkman (AT) ieee (DOT) org

-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On
Behalf Of steve weir
Sent: Monday, May 11, 2009 11:23 AM
To: QU Perry
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Perry, scripts are your friend here.

Best Regards,


Steve.
QU Perry wrote:
> Hi,
>
> I wonder how everyone here creates the model when you try to do a 3D
> EM simulation of PCB related features, do you:
>
> 1. manually create 3D model using the modeler that comes with the
> tool; 2. Use the interface tool provided by EM tool vendor to link to
> PCB or mechanical CAD tool;
>
> I always used option 1 for the following reasons:
> 1. only include features I need so make the model clean and small; 2.
> be able to parameterize and do what if analysis; 3. such 3D simulation


> is usually done in prelayout stage to explore design space so no board


> file is available.
>
> However, I get increasingly tired of doing this as it's a very time
> consuming process. It's no fun to create multi layer PCB and all small
> features such as pads, vias, traces, etc., manually, and each design
> has something different which makes model reuse very difficult.
>
> Was hoping for some kind of wizard tool to let me e.g. create
> multi-layer PCB stackup, define via (pads, antipad etc.) using text
> based dimensions and have the modeler create a PCB model
> automatically, and I can add unique features/structures on top of
> that. That should save a lot of time. Unfortunately not many vendors
> have that option or interested in implementing them (currently using

CST
Microwave Studio).
> I'm aware that Simberor has some of the capability described above but


> then we can't afford getting every new tool in the market.
>
> Regards
>
> Perry
>
> =======================================
>
> Perry Qu
>
> IPD Design & Qualification, Alcatel-Lucent Canada Inc.
>
> 600 March Road, Ottawa ON, K2K 2E6, Canada
>
> DID: 613-7846720 Fax: 613-5993642
>
> Email: perry.qu (AT) alcatel-lucent (DOT) com
>
> =======================================
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property
of
Teraspeed Consulting Group LLC
------------------------------------------------------------------------
----
--------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting
Group
LLC

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Reply With Quote
  #16 (permalink)  
Old 05-11-2009, 11:47 PM
QU Perry
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB modelling wizard ?

Hi, Vittal, Chris:

This is great stuff. Thanks very much ! Now I need to figure out if I
can put it in use for CST. I suppose it should work as I can generate a
HFSS model and then import it into CST. Just I will lose
parameterization. Anyone has tried this ?

This might be a better solution as nothing beats free tool.

Cheers

Perry



=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu (AT) alcatel-lucent (DOT) com
=======================================

-----Original Message-----
From: Chris Herrick [mailto:cherrick (AT) ansoft (DOT) com]
Sent: Monday, May 11, 2009 5:16 PM
To: Vittal.Balasubramanian (AT) fci (DOT) com; QU Perry; asparkman (AT) austin (DOT) rr.com;
weirsi (AT) ipblox (DOT) com
Cc: si-list (AT) freelists (DOT) org
Subject: RE: [SI-LIST] Re: PCB modelling wizard ?

Hello all, as Vittal mentioned, a colleague and I wrote an HFSS Via
Wizard a few years back that's available free on the web. You can
download this from http://3DViaDesign.com. It has a simple GUI where the
user can enter stackup, padstack and via locations. The project is then
generated in HFSS ready solve. I parameterized most of the geometry so
the user can easily optimize the vias. There is no need to be a 3D
modeling expert.

This code is old but still works pretty well. I've recently updated and
enhanced the wizard and will be releasing a new version in the next few
weeks. If anyone has any questions or comments please email me offline.

Thanks,
Chris

-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On Behalf Of Vittal.Balasubramanian (AT) fci (DOT) com
Sent: Monday, May 11, 2009 12:53 PM
To: Perry.Qu (AT) alcatel-lucent (DOT) com; asparkman (AT) austin (DOT) rr.com;
weirsi (AT) ipblox (DOT) com
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Perry,

Ansoft HFSS has a free "via wizard" which does exactly what you need.
You might want to get in touch with them if you do not already have it.

Best regards,
Vittal Balasubramanian
Sr. Signal Integrity Engineer
FCI USA, Inc.


-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On Behalf Of QU Perry
Sent: Monday, May 11, 2009 1:09 PM
To: Aubrey Sparkman; steve weir
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Thanks, Aubrey, Steve.

I guess we need to invest considerable amount of time and effort to get
the scripts done, and I was thinking since such feature are widely
useful for many EM tool users, why can't they do this as this is their
strength ?

In the meanwhile, I will look into the allegro link you mentioned. It's
not as straightforward but should save me some time.

Regards

Perry

=======================================
Perry Qu
IPD Design & Qualification, Alcatel-Lucent Canada Inc.
600 March Road, Ottawa ON, K2K 2E6, Canada
DID: 613-7846720 Fax: 613-5993642
Email: perry.qu (AT) alcatel-lucent (DOT) com
=======================================

-----Original Message-----
From: Aubrey Sparkman [mailto:asparkman (AT) austin (DOT) rr.com]
Sent: Monday, May 11, 2009 12:58 PM
To: 'steve weir'; QU Perry
Cc: si-list (AT) freelists (DOT) org
Subject: RE: [SI-LIST] Re: PCB modelling wizard ?

Perry,

I agree that scripts are certainly the way to go if you do LOTS of 3D
modeling on a continual basis. For others who 3D modeling only at
certain
points in a design cycle, it may be faster to use the interface tool.
Even
for the pre-layout stage (and perhaps because I have some experience
with
Allegro), I find it easier to setup a board and draw the desired
geometry in
Allegro and then transfer it to the 3D tool than to setup a board and
draw
the geometries in the 3D tool. For the post-layout correlation cases,
it's
easy to delete unwanted geometries in Allegro and transfer the
remainder.
Transfer to Momentum is very easy; transfer via Alinks to HFSS or Q3d
has a
couple of bugs you need to watch out for but can be made to work. In
any
case, you can convert specific parts of the design to parameterized
parts
after the transfer.

For your specific needs, you should consider the script development as
an
investment and see which way wins for overall productivity.


Aubrey Sparkman
Aubrey.K.Sparkman (AT) ieee (DOT) org

-----Original Message-----
From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
On
Behalf Of steve weir
Sent: Monday, May 11, 2009 11:23 AM
To: QU Perry
Cc: si-list (AT) freelists (DOT) org
Subject: [SI-LIST] Re: PCB modelling wizard ?

Perry, scripts are your friend here.

Best Regards,


Steve.
QU Perry wrote:
> Hi,
>
> I wonder how everyone here creates the model when you try to do a 3D
> EM simulation of PCB related features, do you:
>
> 1. manually create 3D model using the modeler that comes with the
> tool; 2. Use the interface tool provided by EM tool vendor to link to
> PCB or mechanical CAD tool;
>
> I always used option 1 for the following reasons:
> 1. only include features I need so make the model clean and small; 2.
> be able to parameterize and do what if analysis; 3. such 3D simulation


> is usually done in prelayout stage to explore design space so no board


> file is available.
>
> However, I get increasingly tired of doing this as it's a very time
> consuming process. It's no fun to create multi layer PCB and all small
> features such as pads, vias, traces, etc., manually, and each design
> has something different which makes model reuse very difficult.
>
> Was hoping for some kind of wizard tool to let me e.g. create
> multi-layer PCB stackup, define via (pads, antipad etc.) using text
> based dimensions and have the modeler create a PCB model
> automatically, and I can add unique features/structures on top of
> that. That should save a lot of time. Unfortunately not many vendors
> have that option or interested in implementing them (currently using

CST
Microwave Studio).
> I'm aware that Simberor has some of the capability described above but


> then we can't afford getting every new tool in the market.
>
> Regards
>
> Perry
>
> =======================================
>
> Perry Qu
>
> IPD Design & Qualification, Alcatel-Lucent Canada Inc.
>
> 600 March Road, Ottawa ON, K2K 2E6, Canada
>
> DID: 613-7846720 Fax: 613-5993642
>
> Email: perry.qu (AT) alcatel-lucent (DOT) com
>
> =======================================
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>



--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882

California office
(866) 675-4630 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business
(401) 284-1840 Fax

Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax

http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property
of
Teraspeed Consulting Group LLC
------------------------------------------------------------------------
----
--------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting
Group
LLC

------------------------------------------------------------------
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Reply With Quote
  #17 (permalink)  
Old 05-12-2009, 07:35 AM
viswanathan
Guest
 
Posts: n/a
Default [SI-LIST] Re: PCB modelling wizard ?

Hi All,
Which EDA tool is more accurate for LTCC simulation .I want to know how
AWR is useful for the LTCC simulation .

With Regards
Viswanathan.B

QU Perry wrote:
> Hi, Vittal, Chris:
>
> This is great stuff. Thanks very much ! Now I need to figure out if I
> can put it in use for CST. I suppose it should work as I can generate a
> HFSS model and then import it into CST. Just I will lose
> parameterization. Anyone has tried this ?
>
> This might be a better solution as nothing beats free tool.
>
> Cheers
>
> Perry
>
>
>
> =======================================
> Perry Qu
> IPD Design & Qualification, Alcatel-Lucent Canada Inc.
> 600 March Road, Ottawa ON, K2K 2E6, Canada
> DID: 613-7846720 Fax: 613-5993642
> Email: perry.qu (AT) alcatel-lucent (DOT) com
> =======================================
>
> -----Original Message-----
> From: Chris Herrick [mailto:cherrick (AT) ansoft (DOT) com]
> Sent: Monday, May 11, 2009 5:16 PM
> To: Vittal.Balasubramanian (AT) fci (DOT) com; QU Perry; asparkman (AT) austin (DOT) rr.com;
> weirsi (AT) ipblox (DOT) com
> Cc: si-list (AT) freelists (DOT) org
> Subject: RE: [SI-LIST] Re: PCB modelling wizard ?
>
> Hello all, as Vittal mentioned, a colleague and I wrote an HFSS Via
> Wizard a few years back that's available free on the web. You can
> download this from http://3DViaDesign.com. It has a simple GUI where the
> user can enter stackup, padstack and via locations. The project is then
> generated in HFSS ready solve. I parameterized most of the geometry so
> the user can easily optimize the vias. There is no need to be a 3D
> modeling expert.
>
> This code is old but still works pretty well. I've recently updated and
> enhanced the wizard and will be releasing a new version in the next few
> weeks. If anyone has any questions or comments please email me offline.
>
> Thanks,
> Chris
>
> -----Original Message-----
> From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
> On Behalf Of Vittal.Balasubramanian (AT) fci (DOT) com
> Sent: Monday, May 11, 2009 12:53 PM
> To: Perry.Qu (AT) alcatel-lucent (DOT) com; asparkman (AT) austin (DOT) rr.com;
> weirsi (AT) ipblox (DOT) com
> Cc: si-list (AT) freelists (DOT) org
> Subject: [SI-LIST] Re: PCB modelling wizard ?
>
> Perry,
>
> Ansoft HFSS has a free "via wizard" which does exactly what you need.
> You might want to get in touch with them if you do not already have it.
>
> Best regards,
> Vittal Balasubramanian
> Sr. Signal Integrity Engineer
> FCI USA, Inc.
>
>
> -----Original Message-----
> From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
> On Behalf Of QU Perry
> Sent: Monday, May 11, 2009 1:09 PM
> To: Aubrey Sparkman; steve weir
> Cc: si-list (AT) freelists (DOT) org
> Subject: [SI-LIST] Re: PCB modelling wizard ?
>
> Thanks, Aubrey, Steve.
>
> I guess we need to invest considerable amount of time and effort to get
> the scripts done, and I was thinking since such feature are widely
> useful for many EM tool users, why can't they do this as this is their
> strength ?
>
> In the meanwhile, I will look into the allegro link you mentioned. It's
> not as straightforward but should save me some time.
>
> Regards
>
> Perry
>
> =======================================
> Perry Qu
> IPD Design & Qualification, Alcatel-Lucent Canada Inc.
> 600 March Road, Ottawa ON, K2K 2E6, Canada
> DID: 613-7846720 Fax: 613-5993642
> Email: perry.qu (AT) alcatel-lucent (DOT) com
> =======================================
>
> -----Original Message-----
> From: Aubrey Sparkman [mailto:asparkman (AT) austin (DOT) rr.com]
> Sent: Monday, May 11, 2009 12:58 PM
> To: 'steve weir'; QU Perry
> Cc: si-list (AT) freelists (DOT) org
> Subject: RE: [SI-LIST] Re: PCB modelling wizard ?
>
> Perry,
>
> I agree that scripts are certainly the way to go if you do LOTS of 3D
> modeling on a continual basis. For others who 3D modeling only at
> certain
> points in a design cycle, it may be faster to use the interface tool.
> Even
> for the pre-layout stage (and perhaps because I have some experience
> with
> Allegro), I find it easier to setup a board and draw the desired
> geometry in
> Allegro and then transfer it to the 3D tool than to setup a board and
> draw
> the geometries in the 3D tool. For the post-layout correlation cases,
> it's
> easy to delete unwanted geometries in Allegro and transfer the
> remainder.
> Transfer to Momentum is very easy; transfer via Alinks to HFSS or Q3d
> has a
> couple of bugs you need to watch out for but can be made to work. In
> any
> case, you can convert specific parts of the design to parameterized
> parts
> after the transfer.
>
> For your specific needs, you should consider the script development as
> an
> investment and see which way wins for overall productivity.
>
>
> Aubrey Sparkman
> Aubrey.K.Sparkman (AT) ieee (DOT) org
>
> -----Original Message-----
> From: si-list-bounce (AT) freelists (DOT) org [mailto:si-list-bounce (AT) freelists (DOT) org]
> On
> Behalf Of steve weir
> Sent: Monday, May 11, 2009 11:23 AM
> To: QU Perry
> Cc: si-list (AT) freelists (DOT) org
> Subject: [SI-LIST] Re: PCB modelling wizard ?
>
> Perry, scripts are your friend here.
>
> Best Regards,
>
>
> Steve.
> QU Perry wrote:
>
>> Hi,
>>
>> I wonder how everyone here creates the model when you try to do a 3D
>> EM simulation of PCB related features, do you:
>>
>> 1. manually create 3D model using the modeler that comes with the
>> tool; 2. Use the interface tool provided by EM tool vendor to link to
>> PCB or mechanical CAD tool;
>>
>> I always used option 1 for the following reasons:
>> 1. only include features I need so make the model clean and small; 2.
>> be able to parameterize and do what if analysis; 3. such 3D simulation
>>

>
>
>> is usually done in prelayout stage to explore design space so no board
>>

>
>
>> file is available.
>>
>> However, I get increasingly tired of doing this as it's a very time
>> consuming process. It's no fun to create multi layer PCB and all small
>> features such as pads, vias, traces, etc., manually, and each design
>> has something different which makes model reuse very difficult.
>>
>> Was hoping for some kind of wizard tool to let me e.g. create
>> multi-layer PCB stackup, define via (pads, antipad etc.) using text
>> based dimensions and have the modeler create a PCB model
>> automatically, and I can add unique features/structures on top of
>> that. That should save a lot of time. Unfortunately not many vendors
>> have that option or interested in implementing them (currently using
>>

> CST
> Microwave Studio).
>
>> I'm aware that Simberor has some of the capability described above but
>>

>
>
>> then we can't afford getting every new tool in the market.
>>
>> Regards
>>
>> Perry
>>
>> =======================================
>>
>> Perry Qu
>>
>> IPD Design & Qualification, Alcatel-Lucent Canada Inc.
>>
>> 600 March Road, Ottawa ON, K2K 2E6, Canada
>>
>> DID: 613-7846720 Fax: 613-5993642
>>
>> Email: perry.qu (AT) alcatel-lucent (DOT) com
>>
>> =======================================
>>
>> ------------------------------------------------------------------
>> To unsubscribe from si-list:
>> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>>
>> or to administer your membership from a web page, go to:
>> http://www.freelists.org/webpage/si-list
>>
>> For help:
>> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>>
>>
>> List technical documents are available at:
>> http://www.si-list.net
>>
>> List archives are viewable at:
>> http://www.freelists.org/archives/si-list
>> or at our remote archives:
>> http://groups.yahoo.com/group/si-list/messages
>> Old (prior to June 6, 2001) list archives are viewable at:
>> http://www.qsl.net/wb6tpu
>>
>>
>>
>>
>>

>
>
> --
> Steve Weir
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
>
> California office
> (866) 675-4630 Business
> (707) 780-1951 Fax
>
> Main office
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> Oregon office
> (503) 430-1065 Business
> (503) 430-1285 Fax
>
> http://www.teraspeed.com
> This e-mail contains proprietary and confidential intellectual property
> of
> Teraspeed Consulting Group LLC
> ------------------------------------------------------------------------
> ----
> --------------------------
> Teraspeed(R) is the registered service mark of Teraspeed Consulting
> Group
> LLC
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request (AT) freelists (DOT) org with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request (AT) freelists (DOT) org with 'help' in the Subject field
>
>
> List technical documents are available at:
> http://www.si-list.net
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>
> ------------------------------------------------------------------
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>
> or to administer your membership from a web page, go to:
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>
>
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