FPGA Groups

FPGA Groups (http://www.fpgacentral.com/group/index.php)
-   Newsletter (http://www.fpgacentral.com/group/forumdisplay.php?f=21)
-   -   May 2009 - Xilinx Launches Virtex-5Q FPGA Family for Advanced Defense Systems (http://www.fpgacentral.com/group/showthread.php?t=90732)

Xilinx Newsletter 05-28-2009 01:24 AM

May 2009 - Xilinx Launches Virtex-5Q FPGA Family for Advanced Defense Systems
May 2009   

  Xilinx Launches Virtex-5Q FPGA Family for Advanced Defense Systems
The new Virtex®-5Q family delivers the highest performance, largest capacity FPGAs with ruggedized packaging and advanced cryptographic capabilities. It is the industry's most comprehensive portfolio of defense-grade devices that are also available in bare die form. Visit…

  IEEE Spectrum names Xilinx's first FPGA among “25 Chips that Shook the World”
FPGA Journal covers Xilinx co-founder Freeman's induction into National Inventors Hall of Fame
Xilinx & BEEcube to Unveil Next-Generation FPGA-based Multi-core SoC Development Platform for Sun OpenSPARC

Virtex FPGAs
New On-Demand Webcast: Choosing and Using the Right Transceiver for Serial Interfaces at 3Gbps, 6Gbps, 10Gbps, and Beyond
Learn how to select the proper transceiver for building robust serial interfaces in your next project. In this webcast, we review the capabilities of the 3.125Gpbs GTP transceivers in Spartan®-6 LXT FPGAs, the 6.5Gpbs GTX transceivers in Virtex®®-6 LXT and SXT FPGAs, and the 11.2Gpbs GTH transceivers in Virtex®-6 HXT FPGAs. Using application examples from the wired telecommunications, wireless infrastructure and audio/video broadcast industries, we explore the issues that designers must consider when choosing a serial I/O-enabled FPGA. We will also discuss how to configure these multi-rate transceivers for reliable implementation of serial links based on key interface standards. To learn more and register for the event, visit…
Design Tools
New Webcast: ISE Design Suite 11 - The Design Methodology for Targeted Design Platforms
This on-demand Webcast highlights the ISE® Design Suite 11 as a major milestone in the delivery of targeted design platforms, enabling simpler and smarter design methodologies for creating FPGA-based system-on-chip solutions targeting a wide variety of markets and applications. To view this Webcast now, visit…
New “Embedded Development Kit: Concepts, Tools and Techniques” Now Available
The “Embedded Development Kit: Concepts, Tools and Techniques” has been updated for ISE® Design Suite 11 and is available now on Xilinx.com. This document will show you how to quickly and easily design and build an embedded hardware system. It also covers code development and debug using the Eclipse-based Software Development Kit and features advanced topics including the design of custom peripherals and using the Base System Builder to create dual-processor designs with just a few mouse clicks. Download it now!
New Video: How to Use ISE Simulator (ISim)
A powerful tool within all Editions of the ISE® Design Suite 11, the ISE Simulator provides a complete, full-featured HDL simulator integrated within the ISE Design Suite. This short tutorial video can help you get started quickly. View this and many other ISE Design Suite videos here…
New Video: ISE Design Suite: Logic Edition - A Quick Tour
This video demonstration provides a quick tour of the key highlights and capabilities of the ISE® Design Suite: Logic Edition and how it is used in typical design scenarios. After watching this video, you should have a good understanding of the main steps to get a design through the entire tool chain: from HDL entry, to place and route, all the way through to bit stream generation. View this and many other ISE Design Suite videos here…
The ISE Design Suite: Logic Edition and System Edition Deliver Improvements in Productivity, Performance and Power
The ISE® Design Suite: Logic Edition includes Xilinx® exclusive tools and technologies to help you achieve optimal design results in less time. These include PlanAhead for advanced FPGA floorplanning, ChipScope Pro for in-circuit verification, and SmartGuide for faster incremental implementation. To find out what’s new for logic and connectivity developers in the ISE Design Suite, visit...
ISE Design Suite: DSP Edition Delivers Faster DSP Performance, Improved Integration and Expanded Platform Support
The ISE® Design Suite: DSP Edition includes all of the features and technologies found in the ISE Design Suite: Logic Edition plus additional tools and DSP-specific IP tailored to the needs of algorithm, system, and hardware developers. Find out what’s new for DSP developers in the ISE Design Suite online.
ISE Design Suite: Embedded Edition Simplifies the Solution for Designing Embedded Processing Systems
The ISE® Design Suite: Embedded Edition includes all of the features and technologies found in the ISE Design Suite: Logic Edition plus additional tools and IP required for Xilinx® Platform FPGAs designs with embedded PowerPC® hard processor cores and/or MicroBlaze™ soft processor cores. Find out what’s new for embedded developers in the ISE Design Suite online.
Embedded Processing
Live Xilinx Webinar on June 23, 2009--Direct Memory Access (DMA) on Xilinx Virtex®-6 and Spartan-6 PCI Express
This web seminar shows how Xilinx® offers the key components to take advantage of integrated PCI EXPRESS® block support for increased chip-to-chip bandwidth in Virtex®-6 and Spartan®-6 FPGAs. Registration opening soon on our webcast site.
Aerospace & Defense
NASA uses Virtex®-4 in Hubble Repair Mission
Xilinx is very proud to announce that NASA engineers are using commercial grade Virtex®-4 FX60 FPGAs in the Hubble Space Telescope repair mission STS-125 launched on May 11, 2009. In particular, the FPGAs are at the heart of a powerful computer, dubbed the SpaceCube, in shuttle Atlantis’ support equipment. According to NASA technologist David Petrick, the SpaceCube-- which leverages redundant computing cores (eight PowerPC cores embedded in four commercial grade Virtex-4 FPGAs)--performed flawlessly. The SpaceCube's position on the MULE (Multi-Use Lightweight Equipment) carrier can be seen in Fig. 2-7 of the mission media guide available here in this 28 MB pdf download.
Xilinx Aerospace and Defense to Attend Military Aerospace Electronics Forum
Xilinx® will be showcasing the newly introduced defense-grade Virtex®-5Q FPGAs and demonstrating an Avionics Certifiable Hardware/Software Platform, including DO-254 capable Virtex-5 FPGAs operating with a safety-critical LynuxWorks LynxOS-178 RTOS. Please contact your local sales team to arrange for a meeting with Xilinx's Aerospace and Defense team while at the show. For more information about aerospace and defense, visit…
Visit Xilinx at the Intel Embedded eVent - Event Archive Now Available!
Learn how Xilinx® and Intel are delivering levels of performance, scalability, and flexibility not previously available on an open infotainment platform (OIP) – while accelerating system development. Event in-depth demonstrations will highlight Xilinx automotive flexible connectivity to the low-power Intel® In-Vehicle Infotainment (IVI) evaluation design targeted at high-end automotive head units. Attend the event at…
Services, Events & Education
ISE Design Suite 11.1 Training Now Available
Log on to your local Xilinx training provider’s website and register for ISE® Design Suite 11.1 training for the following classes: Essentials of FPGA Design (formerly Fundamentals of FPGA Design), Designing for Performance, Advanced FPGA Implementation, DSP Design Using System Generator, ISE Design Tool Flow, Embedded Systems Development. More 11.1 classes will be available in June. Check with the Xilinx Authorized Training Provider in your region for the latest information. For the training provider in your region, visit…
Live Partner Webinar on June 11, 2009 from Agilent- New Scope Technology Accelerates FPGA Debug
FPGAs have become the centerpiece of digital design. With superior analog, digital and new protocol analysis capabilities, the Infiniium oscilloscope lineup was designed to be the go-to tool for debugging and testing FPGAs. Agilent will show measurement examples using designs that incorporate Xilinx® FPGAs. Register for the Agilent Web Seminar here…
Avnet Electronics and Xilinx Announce X-fest - Full Day Technical Seminars Delivered in 36 Cities Worldwide
From October 2009 through February 2010, Avnet and Xilinx will co-host X-fest events in 36 locations throughout Asia, Europe, North America and Japan. X-fest is a global series of technical seminars - offering practical, how-to training for designers interested in using the new Spartan®-6 and Virtex®-6 FPGA families from Xilinx. X-fest events will also feature partner exhibits that allow for direct interaction with factory experts eager to share their insights into exciting new products and advanced technologies and to demonstrate the latest development platforms. Read more, learn about the participating partners and register for an event near you!
Xilinx Partner Spotlight
X-Tech - Xilinx announces Technical Seminars in the Pacific Northwest
Xilinx and its partners are pleased to announce the X-Tech 2009 Technical Seminar series is headed to the Pacific Northwest. X-Tech is a free, one day technical seminar focused on topics important to hardware engineers, software engineers, and system architects. These multi-track events have sessions for every type of designer who works in British Columbia Canada, Washington or Oregon USA. The seminar includes food and beverage but to attend, you must register prior to the seminars. X-Tech will be held in Burnaby, BC Canada on June 2, 2009, in Lynnwood, WA on June 3 and Lake Oswego, OR on June 4.
©1994-2009 Xilinx, Inc. All Rights Reserved
Your California Privacy Rights | Xilinx Privacy Statement

This email was sent to newsletter (AT) list (DOT) fpgacentral.com
To no longer receive emails from Xilinx, please click here.

Xilinx, Inc. - 2100 Logic Drive, San Jose, CA 95124-3400 - USA

All times are GMT +1. The time now is 02:07 AM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2019, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved