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IC Designs and Verification requirement in India, Bangalore abdul	12-03-2003 09:33 PM by Andy Peters	1	232
gvim 6.0 versus gvim 6.2 pini	11-26-2003 07:58 AM by pini	0	166
Verilog Sequential Multiplier Peter Laquidara	12-01-2003 08:49 PM by Peter Laquidara	0	297
Implementation of parallel 2D median filtering Andreas	12-02-2003 10:44 AM by Andreas	0	275
CFP: 7th Mil/Aerospace Applications of Programmable Logic Devices International Conference (MAPLD) Richard B. Katz	12-04-2003 06:08 AM by Richard B. Katz	0	284
Updating global reg's from inside functions/tasks Jay Bhadra	11-18-2003 10:30 PM by Steven Sharp	1	300
Debussy/nCompare users? chad.robinson	11-14-2003 09:11 AM by YC Su	1	514
SystemC reco needed! ravi	11-08-2003 02:42 AM by Kim Hyun-Gyu	1	239
how can verilog use mem in maxplus? ZZZzzz	11-09-2003 12:18 PM by ZZZzzz	0	191
Return value for $fscanf on EOF. John	11-18-2003 06:37 PM by Steven Sharp	3	1,323
Need to verify an ATA/ATAPI-6 device Fred	11-12-2003 02:18 PM by Fred	0	220
Can't find companion website for the "Ciletti" Verilog book. Teece	11-12-2003 05:55 PM by John_H	1	416
gtk wave -two how to questions pini	11-22-2003 10:21 PM by Anthony J Bybell	12	438
Help with $setuphold syntax Paul Richardson	11-14-2003 11:07 PM by David Roberts	1	628
Entry Level position in VLSI Design or EDA Industry Vishal	11-14-2003 01:07 AM by Vishal	0	298
Reading back SRAM content via JTAG? moe	11-16-2003 02:22 PM by Jim Wu	3	251
anybody can help me write a DCT module? walala	11-19-2003 04:48 PM by Swapnajit Mittra	1	212
Verilog Netlest Reader Code, ATPG Code Robert Posey	11-19-2003 11:41 PM by Robert Posey	0	518
problem running icarus verilog 0.7 - "target_design entry point is missing" malexgreen	11-20-2003 06:03 AM by malexgreen	0	1,063
verification vs validation pradeep	11-30-2003 04:55 AM by Jason Doege	3	188
Asynchrous reset. One Day & A Knight	11-21-2003 09:45 AM by Muzaffer Kal	1	738
Console I/O?? JT	11-21-2003 10:12 PM by Alexander Gnusin	3	282
Tyd-IP Code Generator....VHDL for DSP Michael Gallen	11-25-2003 12:15 AM by Michael Gallen	0	205
diagraming tool for verilog code Mike	11-05-2003 04:30 PM by Mike	0	205
latch and shift 15 bits. Denis Gleeson	11-08-2003 06:59 PM by Nate Goldshlag	5	446
How to make assign with large delay? Patrick Phung	11-05-2003 09:05 PM by Jonathan Bromley	2	350
Use of #delay_value in synchronous processes? JT	11-06-2003 11:40 PM by Jonathan Bromley	7	277
goto statement is recommened in systemc? youngsun park	11-18-2003 03:47 PM by David Pursley	2	238
Parallel if statement in clocked block Kiran	11-08-2003 01:05 AM by Gregorio Gervasio, Jr.	14	298
PLI: manipulating reg data through VPI Girish Venkataramani	11-17-2003 10:09 PM by Chris F Clark	4	292

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