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Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or... Weng Tianxiang	09-22-2007 05:06 AM by Weng Tianxiang	0	201
Default input value [email protected]	09-21-2007 05:39 PM by Kevin Neilson	2	185
Cycle Accurate Modelling designer	09-21-2007 10:15 AM by designer	0	223
query ram	09-19-2007 06:16 AM by John_H	1	432
query ram	09-19-2007 03:34 AM by ram	0	336
ANNC: PCI Express and Ethernet Gaskets Webcasts bart	09-18-2007 10:50 PM by bart	0	154
Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or... Weng Tianxiang	09-21-2007 06:32 PM by Hal Murray	9	187
Compiler identification manifest constants? Evan Lavelle	09-20-2007 06:10 PM by [email protected]	3	159
Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or... Weng Tianxiang	09-18-2007 08:01 PM by glen herrmannsfeldt	2	227
Is this wrong behavior? Neo	09-20-2007 05:49 AM by glen herrmannsfeldt	7	481
[ANNOUNCE] YARDstick - custom processor development toolset Uncle Noah	09-21-2007 02:26 AM by Uncle Noah	12	256
does ncsim supports PLI2.0 Ramesh	09-17-2007 03:27 PM by David Roberts	1	153
How to write top module [email protected]	09-17-2007 02:20 PM by [email protected]	1	225
vpi_put_value SrFPGA	09-17-2007 03:19 PM by David Roberts	4	160
Among the variable types in Verilog, which are signed [email protected]	09-21-2007 11:46 PM by [email protected]	3	216
Determining width of a variable? Evan Lavelle	09-13-2007 09:28 AM by Jonathan Bromley	9	194
Verilog-AMS timer Paul Floyd	09-12-2007 08:30 PM by Paul Floyd	0	235
Conditional wait statement in a verilog testbench kb33	09-21-2007 06:49 PM by [email protected]	7	314
a question about fsm confusing me for a long time anny	09-12-2007 11:35 PM by Andy	2	155
Bit utility macros Evan Lavelle	09-20-2007 04:14 PM by Evan Lavelle	2	214
Verilog LRM Anand	09-12-2007 12:15 PM by Petter Gustad	1	211
"Latch generated" warning from Synplicity kb33	09-14-2007 08:55 PM by [email protected]	9	528
64-bit wide multiple port instances Jake	09-11-2007 11:06 PM by John_H	3	224
SV: How to "import" an interface into a module w/o `include? mrfirmware	09-12-2007 05:36 PM by Jonathan Bromley	12	183
Neural networks in VHDL [email protected]	09-11-2007 07:55 PM by Mike Treseler	1	243
What is called carry chain structure in FPGA is called in IC? Weng Tianxiang	09-12-2007 08:19 AM by glen herrmannsfeldt	6	169
What is the name of Altera latest and most advanced chip serial that is competable in technology with Vertex V in terms of system strucute(LUT6...) Weng Tianxiang	09-11-2007 01:42 AM by Weng Tianxiang	2	191
inout port instantiation in top level structural module kb33	09-12-2007 05:32 AM by [email protected]	1	184
Strings in Verilog [email protected]	09-19-2007 06:54 PM by Kevin Neilson	3	2,388
How to code integration in verilog yeah	09-17-2007 02:14 PM by IDDLife	2	899

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