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Divide by 3/2 clock generation with 50% duty cycle? rsk	07-25-2005 08:36 PM by [email protected]	7	10,407
evcd file format swang1	12-07-2009 11:43 AM by avinashthakare	4	7,076
difference between $fwrite and $fdisplay in verilog ramnarayan	03-01-2007 01:47 PM by [email protected]	1	4,613
Port mode is incompatible error [email protected]	10-19-2006 08:44 AM by Mark McDougall	5	4,174
Verilog ternary operator Sailu	09-08-2007 12:02 AM by glen herrmannsfeldt	2	3,714
SystemVerilog cross-module reference resolution error [email protected]	03-21-2007 04:04 AM by [email protected]	0	3,124
how to exclude signals from $fsdbDumpvars [email protected]	04-25-2007 09:56 AM by [email protected]	0	3,035
Illegal reference to net maTheMatic	11-28-2004 05:04 PM by Swapnajit Mittra	4	2,936
Writing a binary file in Verilog Charles Bailey	10-07-2004 01:57 PM by Charles Bailey	9	2,873
wholesale NFL,NBA,MLB Jersey big123abcd	11-02-2009 05:04 PM by big123abcd	0	2,765
Simple PS/2 Keyboard John	06-01-2004 04:43 PM by Jeremy Webb	8	2,740
Nested generate statement problems Douglas Maxwell	08-12-2003 01:21 PM by Jonathan Bromley	1	2,686
how to simulate verilog with rom in modelsim? seanzhang	09-11-2004 01:35 AM by pablo aimar	6	2,686
Hash Table prasunp	05-07-2006 09:17 PM by Jeremy Ralph	5	2,593
Encrypting verilog files Arturi	04-04-2005 05:31 PM by Keith	17	2,582
Assert in verilog DW	05-20-2004 03:57 PM by DW	7	2,495
Question about arithmetic right shift with sign extension pallav	05-05-2009 11:57 PM by [email protected]	4	2,485
Simvision, how may I make it automatically convert a VCD file into TRN? Kelvin	11-22-2004 01:11 AM by Kelvin	5	2,424
Strings in Verilog [email protected]	09-19-2007 06:54 PM by Kevin Neilson	3	2,388
Where to shop lingeries? SERGIO456	03-20-2012 12:04 PM by SERGIO456	0	2,348
How to Divide a clock by 2 [email protected]	02-17-2006 05:10 AM by Art Stamness	8	2,297
implementing a ping-pong buffer anon	03-09-2007 02:38 PM by anon	0	2,289
A synthesis question about "high-fanout nets" walter	07-04-2003 05:30 PM by walter	3	2,277
protect/endprotect & verilog 2001 Eric Peterson	02-02-2005 12:20 AM by [email protected]	7	2,258
2x Clock Multiplier Help GamEmpire	04-02-2009 03:45 AM by hairyotter	2	2,255
Have question regarding parameter usage in verilog Veeresh	07-09-2009 05:47 PM by Veeresh	2	2,191
System Verilog:-streaming operator varsha	03-06-2009 04:27 PM by Jonathan Bromley	1	2,169
SystemVerilog: how to attach an SV interface within a VHDL DUT Andrew FPGA	02-24-2010 01:09 AM by Andrew FPGA	13	2,130
C structs in Verilog ? Daku	10-18-2009 03:37 AM by Daku	2	2,110
Hex start address in $readmemh? Muzaffer Kal	03-29-2009 06:14 AM by pallav	1	2,039

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