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Old 04-16-2006, 07:33 PM
Jeff Brower
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Default XST not inferring distributed RAM

All-

I cannot seem to coax XST to infer a distributed RAM -- I believe it
should find a simple, single-port, asynchronous read instance, but I
continue to get the dreaded rejection notice "N flip-flops were
inferred for signal <mem>. You may be trying to describe a RAM in a way
that is incompatible with block and distributed RAM resources available
on Xilinx devices..."

I have included a simplified version of my code below.

Is the word "assign" necessary for output? I would think not since
the output is still continuous / combinatorial.

If anyone has suggestions for key syntax that I'm missing...

-Jeff

reg [1:0] index;
reg [3:0] mem [3:0]; /* declare RAM to hold series of 4-pin IO array
values */
integer i, j;

always @(posedge clk) begin /* store mem values */

if (reset)
index = 0;
else
index = index + 1;

for (i=0; i<4; i=i+1)
mem[i][index] <= IO_array[i];
end


/* use mem values */

always @( id[0], id[1], id[2], id[3],
mem[0], mem[1], mem[2], mem[3],
st_num,
mem_index
) begin

for (i=0; i<4; i=i+1) begin
for (j=0; j<4; j=j+1) begin

table[i][j] = st_num ? mem[id[i]][mem_index] :
mem[id[i]][mem_index];
end
end
end

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  #2 (permalink)  
Old 04-17-2006, 03:27 AM
JustJohn
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Default Re: XST not inferring distributed RAM

Jeff Brower wrote:
> All-
>
> I cannot seem to coax XST to infer a distributed RAM -- I believe it
> should find a simple, single-port, asynchronous read instance, but I
> continue to get the dreaded rejection notice "N flip-flops were
> inferred for signal <mem>. You may be trying to describe a RAM in a way
> that is incompatible with block and distributed RAM resources available
> on Xilinx devices..."
>> If anyone has suggestions for key syntax that I'm missing...

>
> -Jeff
>
> reg [1:0] index;
> reg [3:0] mem [3:0]; /* declare RAM to hold series of 4-pin IO array
> values */
> integer i, j;
>
> always @(posedge clk) begin /* store mem values */
>
> if (reset)
> index = 0;
> else
> index = index + 1;
>
> for (i=0; i<4; i=i+1)
> mem[i][index] <= IO_array[i];
> end
> end


Jeff, I'm not a Verilog guy, but my first suggestion is that your index
order is reversed. With a memory array, the index nearest the
identifier is the address, while the outer index addresses the bits of
the vectors in the array.
You may also be able to simplify things by skipping the bit iterations
altogether and writing something like:

always @(posedge clk) begin /* store mem values */
if (reset)
index = 0;
else
index = index + 1;
mem[index] <= IO_array;
end

(only showing write function for brevity)
The code you wrote was iterating over all addresses in the array in a
single cycle, which a memory cannot do, so you get a lot of
registers....

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  #3 (permalink)  
Old 04-17-2006, 03:29 PM
Jeff Brower
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Default Re: XST not inferring distributed RAM

John-

> The code you wrote was iterating over all addresses in the array in a
> single cycle, which a memory cannot do, so you get a lot of
> registers....


I had wanted to store the IO values "vertically", each column
representing a bit-cell, because the IO pins carry multiple parallel
bitstreams... but based on your advice I stored them horizontally and
re-arranged other code to match. And that did work -- although I ended
up with several distributed RAMs inferred, because read accesses occur
in various ways.

But it does save one heck of a lot of flip-flops and at least I've a
grip now on how XST wants to deal with distributed RAM... thanks John.

-Jeff

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