FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-19-2006, 03:53 PM
Jeff Brower
Guest
 
Posts: n/a
Default XST issues with loop code

All-

I had posted before about XST not generating correct netlist for
comparisons inside nested loop code within an always block. The code
is of this form:

always @( a[0], a[1], a[2], ... ) begin

for (i=0; i<32; i++) begin

for (j=0; j<32; j++) begin

if (a[j][4:0] == i) begin

if (a[j][28:27] == 2'd2) <-- comparison

b1[i][j] = 1'b1;

else

b2[i][j] = 1'b1;
end
else begin
b1[i][j] = 1'b0;
b2[i][j] = 1'b0;
end
end
end
end

What I found for the following ways to do the innermost comparison:

if (a[j][28:27] == 2) <--- crashes XST

if (a[j][28:27] == 2'd2) <--- doesn't crash XST, but generates
incorrect netlist

if (((a[j][28:27] & 32'h03000000) >> 28) = 2) <--- generates correct
netlist, works

Results were the same whether I used while loops (see XST answer
records 22625 and 22066) or used a genvar for the outer loop (outside
the always block).

This is with XST 7.1i. From the answer records about XST issues with
loop code, I might guess this problem could persist a while, possibly
through 9.1i or longer. I thought I would put this up for future
reference, in case anyone else runs into the same thing.

-Jeff

Reply With Quote
  #2 (permalink)  
Old 04-19-2006, 04:22 PM
John_H
Guest
 
Posts: n/a
Default Re: XST issues with loop code

The problem might go away sooner if this was submitted as a web case!
I know of *no* authors of EDA tools that want incorrect logic in their code.
Usability is one thing, bad results are another.

"Jeff Brower" <[email protected]> wrote in message
news:[email protected] oups.com...
> All-
>
> I had posted before about XST not generating correct netlist for
> comparisons inside nested loop code within an always block. The code
> is of this form:
>
> always @( a[0], a[1], a[2], ... ) begin
>
> for (i=0; i<32; i++) begin
>
> for (j=0; j<32; j++) begin
>
> if (a[j][4:0] == i) begin
>
> if (a[j][28:27] == 2'd2) <-- comparison
>
> b1[i][j] = 1'b1;
>
> else
>
> b2[i][j] = 1'b1;
> end
> else begin
> b1[i][j] = 1'b0;
> b2[i][j] = 1'b0;
> end
> end
> end
> end
>
> What I found for the following ways to do the innermost comparison:
>
> if (a[j][28:27] == 2) <--- crashes XST
>
> if (a[j][28:27] == 2'd2) <--- doesn't crash XST, but generates
> incorrect netlist
>
> if (((a[j][28:27] & 32'h03000000) >> 28) = 2) <--- generates correct
> netlist, works
>
> Results were the same whether I used while loops (see XST answer
> records 22625 and 22066) or used a genvar for the outer loop (outside
> the always block).
>
> This is with XST 7.1i. From the answer records about XST issues with
> loop code, I might guess this problem could persist a while, possibly
> through 9.1i or longer. I thought I would put this up for future
> reference, in case anyone else runs into the same thing.
>
> -Jeff
>



Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
for loop with access to a ROM [email protected] Verilog 2 04-25-2008 10:06 PM
Parametrized for loop crazydubi Verilog 3 10-25-2006 10:54 PM
Loop Optimization Roberto FPGA 0 02-25-2006 01:51 PM
using the for-loop ! hanson j FPGA 0 03-24-2005 02:48 PM
`define within a for loop ric Verilog 0 02-02-2004 07:14 AM


All times are GMT +1. The time now is 06:55 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved