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  #1 (permalink)  
Old 04-06-2004, 02:29 PM
Edward
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Default XPower: Post-Place and Route Simulation model

Hi All,

I am currently using XPower 5.2.03i with Modelsim 5.7d. To ensure that
the actual low-level design is condidered, I used the post place and
route Simulation model (i.e. vhd file generated in Project Navigator)
to generate a vcd file in modelsim.

The power estimate that results is far larger than that power
measurements made on hardware for the same set of inputs. Could it be
due to the fact that the model instead of the original high-level vhdl
files are used in the simulation in Modelsim. If so, what is the
remedy that would consider all the low-level aspects of the design
aside from adding the *.sdf file during modelsim simulation as well as
taking into account all nets.

Thanks a mil!

Ed
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  #2 (permalink)  
Old 08-08-2006, 12:38 PM
Johannes Hausensteiner
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Default Newbie question

Hi there,

I am doing my first FPGA/VHDL design. Previously I did CPLD designs
utilizing Altera's AHDL.
I coded the VHDL source files and simulated it successfully with
Modelsim. Then I made the I/O pin assignments and made the .bit
file and loaded it to the FPGA. To my disappointment only some of
the signals are correct; the functionality of the system does not
work.
I am using ispLEVER and a Lattice LFEC33 FPGA.
There is a "Post Place and Route Simulation" action available within
ispLEVER (actually it starts Modelsim), but this does not work.
Modelsim always complains "Error loading design".
What possibilities do I have to debug my design?

Thanks a lot,

Johannes
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Old 08-08-2006, 02:28 PM
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Default Re: Newbie question

Hi Johannes,

did you import the testbench file and associate it to the device in
ispLEVER?
By doing that you can start functional and timing simulation when
marking
the device.

Besides are you using VHDL packages ?

Rgds
André


> There is a "Post Place and Route Simulation" action available within
> ispLEVER (actually it starts Modelsim), but this does not work.
> Modelsim always complains "Error loading design".
> What possibilities do I have to debug my design?
>
> Thanks a lot,
>
> Johannes


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  #4 (permalink)  
Old 08-08-2006, 03:21 PM
Mike Treseler
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Default Re: Newbie question

Johannes Hausensteiner wrote:

> I am doing my first FPGA/VHDL design.
> I coded the VHDL source files and simulated it successfully with
> Modelsim. Then I made the I/O pin assignments and made the .bit
> file and loaded it to the FPGA. To my disappointment only some of
> the signals are correct; the functionality of the system does not
> work.
> I am using ispLEVER and a Lattice LFEC33 FPGA.
> There is a "Post Place and Route Simulation" action available within
> ispLEVER (actually it starts Modelsim), but this does not work.
> Modelsim always complains "Error loading design".


Use modelsim directly from the command line or GUI.

> What possibilities do I have to debug my design?


Common first-time synthesis problems include:
Use of wait statements.
No clock.
No reset.
Inputs not synchronized.
Clock or reset on non-global pin.
Not using standard clocked process template.

If all else fails,
post your code to comp.lang.vhdl
Good luck.

-- Mike Treseler
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  #5 (permalink)  
Old 08-08-2006, 08:08 PM
bart
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Default Re: Newbie question

Johannes Hausensteiner wrote:

> What possibilities do I have to debug my design?


Hi Johannes,
besides comp.arch.fpga and other usenet groups, you could post your
questions on Lattice's support forum:

http://www.latticesemi.com/support/forums.cfm

hope this helps.
regards,
bart borosky, lattice

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  #6 (permalink)  
Old 08-09-2006, 03:16 PM
Johannes Hausensteiner
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Default Re: Newbie question

Hi Bart,

Thanks for the link.

bart wrote:
> Johannes Hausensteiner wrote:
>
>> What possibilities do I have to debug my design?

>
> Hi Johannes,
> besides comp.arch.fpga and other usenet groups, you could post your
> questions on Lattice's support forum:
>
> http://www.latticesemi.com/support/forums.cfm
>
> hope this helps.
> regards,
> bart borosky, lattice
>

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  #7 (permalink)  
Old 08-09-2006, 03:16 PM
Johannes Hausensteiner
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Default Re: Newbie question

Hi André,

Thanks for your answer; yes I added my testbench to the ispLEVER
project and assosiated it to the FPGA chip. I get three entries in
right pane of the ispLEVER ProjectNavigator:
- VHDL Functional Simulation
- VHDL Post-Route Functional Simulation
- VHDL Post-Route Timing Simulation
When I double-click on any of them Modelsim is started and it compiles
and tries to load the design. In all three of them there are following
error messages in Modelsim:
-- snip ---
# ** Error: (vsim-3170) Could not find 'work.StimModule_Unknown'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
-- snip ---
The name "work.StimModule_Unknown" is used for each and every design
I tried up to now.
When I replace this in the (by ispLEVER generated) do-files
(test_bench.fdo, test_bench.xdo, test_bench.tdo) with the name of the
testbench then the "Functional Simulation" will work.
The "Post-Route Functional Simulation" and the "Post-Route Timing
Simulation" will still refuse to load in Modelsim with the following
error:
-- snip ---
# Loading work.tb_counter(test_counter)
# ** Error: (vsim-13) Recompile work.counter(everything) because
work.counter has changed.
# Error loading design
# Error: Error loading design
-- snip ---
This does not change when I actually recompile "counter",
"work.counter", or the whole design.

While once more double-checking I found out the following:
for the "Post-Route ... Simulation" ispLEVER decompiles what it has
routed to a VHDL file named "design.vho". This uses the architecture
name "Structure". For the testbench to be loaded correctly within
Modelsim is has (of course) to be of architecture "Structure", too
(which was in the case in my design). - OK, this one is clear; I can
live with the "work.StimModule_Unknown" thing.


So thank you for your replies!

Johannes



[email protected] wrote:
> Hi Johannes,
>
> did you import the testbench file and associate it to the device in
> ispLEVER?
> By doing that you can start functional and timing simulation when
> marking
> the device.
>
> Besides are you using VHDL packages ?
>
> Rgds
> André
>
>
>> There is a "Post Place and Route Simulation" action available within
>> ispLEVER (actually it starts Modelsim), but this does not work.
>> Modelsim always complains "Error loading design".
>> What possibilities do I have to debug my design?
>>
>> Thanks a lot,
>>
>> Johannes

>


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