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  #1 (permalink)  
Old 11-21-2003, 01:36 PM
Fred
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Posts: n/a
Default Xlilinx (xc2vp30-5fg676)


I have a problem I hope someone here can give an answer to:

I'm working on my first project for a Xilinx Virtex II Pro FPGA,
and I'm having some problems with simulation results I get
when simulating on the "post place and route" VHDL model.

Actually the strange behavioir (which I suppose isn't strange
at all, if I only knew how things worked) appears in all simulations
other then when I simulate on the behavioural model.

The "strange behaviour" I'm refering to, is that no matter what
I do, I cannot get anything (other than 0) on my output untill a
sertain time has passed by.

To simulate, I start Modelsim from Xilinx Project navigator.

Now I have made a test-project, only containing a 8 bit register
between the input and output pins, and I'm still experiencing this
behaviour. I've made a ASCII-drawing of the sim-result that can
be found at the bottom of my post.

My question is: Is there a certain time that the FPGA need to
complete internal resets and such, that is actually reflected in
the simulation for all other simulations than on the behavioural
model? If so, where in the spec is this specified? What is it
called, etc.

Sincerely
-Fred, Norway.


ASCII-figure:
Remember to view it in a monospace font:

+-----------------------------------------+
| Post PAR simulation |
+-----------------------------------------+
| Problem: Nothing but 0 on my outputs |
| until the 6th clk period. |
+-----------------------------------------+
| |
|0 ns 100 ns |
|| 20 ns |110 ns |
|| | | | |
| _ _ _ _ _ _ _ _ _ _ |
|_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_|
| |
| __ __ __ __ |
|_____________________/A \/B \/C \/D \____|
| \__/\__/\__/\__/ |
| __ __ __ __ |
|______________________/A \/B \/C \/D \___|
| \__/\__/\__/\__/ |
| |
| __ __ __ __ |
|_________________/A \/B \/C \/D \________|
| \__/\__/\__/\__/ |
| __ __ __ |
|______________________/B \/C \/D \_______|
| \__/\__/\__/ |
| |
| __ __ __ __ |
|_____________/A \/B \/C \/D \____________|
| \__/\__/\__/\__/ |
| __ __ |
|______________________/C \/D \___________|
| \__/\__/ |
| |
| __ __ __ __ |
|_________/A \/B \/C \/D \________________|
| \__/\__/\__/\__/ |
| __ |
|______________________/D \_______________|
| \__/ |
| |
+-----------------------------------------+
| FPGA: Virtex II Pro (xc2vp30-5fg676) |
| Sim: Modelsim XE II 5.7c |
+-----------------------------------------+
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  #2 (permalink)  
Old 11-21-2003, 01:41 PM
Fred
Guest
 
Posts: n/a
Default New ASCII-figure

I forgot to name my signals, so here is a new ASCII-figure:

+-----------------------------------------+
| Post PAR simulation |
+-----------------------------------------+
| Problem: Nothing but 0 on my outputs |
| until the 6th clk period. |
+-----------------------------------------+
| |
|0 ns 100 ns |
|| 20 ns |110 ns |
|| | | | |
| _ _ _ _ _ _ _ _ _ _ |
|_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_|
| |
|IN_1 __ __ __ __ |
|_____________________/A \/B \/C \/D \____|
| \__/\__/\__/\__/ |
|OUT_1 __ __ __ __ |
|______________________/A \/B \/C \/D \___|
| \__/\__/\__/\__/ |
| |
|IN_2 __ __ __ __ |
|_________________/A \/B \/C \/D \________|
| \__/\__/\__/\__/ |
|OUT_2 __ __ __ |
|______________________/B \/C \/D \_______|
| \__/\__/\__/ |
| |
|IN_3 __ __ __ __ |
|_____________/A \/B \/C \/D \____________|
| \__/\__/\__/\__/ |
|Out_3 __ __ |
|______________________/C \/D \___________|
| \__/\__/ |
| |
|IN_4 __ __ __ __ |
|_________/A \/B \/C \/D \________________|
| \__/\__/\__/\__/ |
|OUT_4 __ |
|______________________/D \_______________|
| \__/ |
| |
+-----------------------------------------+
| FPGA: Virtex II Pro (xc2vp30-5fg676) |
| Sim: Modelsim XE II 5.7c |
+-----------------------------------------+
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  #3 (permalink)  
Old 11-21-2003, 01:44 PM
Fred
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Posts: n/a
Default Re: New ASCII-figure

Crap. This was supposed to be a follow up on
my other thread. Sorry for the inconvenience...

-Fred

P.S. If anyone has a good news-client to
recommend, please do
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  #4 (permalink)  
Old 11-22-2003, 09:10 AM
Philip Freidin
Guest
 
Posts: n/a
Default Re: New ASCII-figure

On Fri, 21 Nov 2003 13:44:18 GMT, Fred <[email protected]> wrote:
>Crap. This was supposed to be a follow up on
>my other thread. Sorry for the inconvenience...
>
>-Fred
>
>P.S. If anyone has a good news-client to
>recommend, please do


Unfortunately, with your spam blocking email address, I could
not reply off-list.

I have used Forte Agent for several years for both email and
news groups, and it meets all my needs. A free version with
somewhat less features is also available. Best of all, it
does not understand HTML, and so it is totally tolerant of
viruses, worms, etc.

http://www.forteinc.com/main/homepage.php

Philip


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