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Old 02-06-2004, 10:43 PM
Peter Horst
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Default Xilinx WARNING:NetListWriters:117

Hello,

I'm getting the following warning when implementing my design using
Xilinx Alliance M1.3 tools:

WARNING:NetListWriters:117 - Signal S_CTRL_PC_CONTROL(2) not found for
signal
bus S_CTRL_PC_CONTROL( 3 downto 1 ) on block CPU.
WARNING:NetListWriters:107 - Signal bus S_CTRL_PC_CONTROL( 3 downto 1
) on
block CPU is not reconstructed.

My gate level simulation is not working and I suspect these types of
warnings are the culprits (I get several of these warnings for
different signals). Does any one have any hints?

Thanks,

Peter
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  #2 (permalink)  
Old 02-06-2004, 11:56 PM
Eric Crabill
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Default Re: Xilinx WARNING:NetListWriters:117


Hi,

This is probably not your issue. Let's say your
S_CTRL_PC_CONTROL bus has one of the bus signals
tied to a constant. These get optimized away in
the physical implementation.

When you write out a simulation netlist afterwards,
the netlist writer tool is letting you know, "Hey,
I can't find this net anymore..." and that it cannot
reconstruct the complete bus. However, it should
still simulate correctly.

Eric

Peter Horst wrote:
>
> Hello,
>
> I'm getting the following warning when implementing my design using
> Xilinx Alliance M1.3 tools:
>
> WARNING:NetListWriters:117 - Signal S_CTRL_PC_CONTROL(2) not found for
> signal
> bus S_CTRL_PC_CONTROL( 3 downto 1 ) on block CPU.
> WARNING:NetListWriters:107 - Signal bus S_CTRL_PC_CONTROL( 3 downto 1
> ) on
> block CPU is not reconstructed.
>
> My gate level simulation is not working and I suspect these types of
> warnings are the culprits (I get several of these warnings for
> different signals). Does any one have any hints?
>
> Thanks,
>
> Peter

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